Datasheet

DocID027590 Rev 4 165/227
STM32F745xx STM32F746xx Electrical characteristics
195
Figure 54. ULPI timing diagram
Table 83. USB HS clock timing parameters
(1)
1. Guaranteed by design.
Symbol Parameter Min Typ Max Unit
-
f
HCLK
value to guarantee proper operation of
USB HS interface
30 - - MHz
F
START_8BIT
Frequency (first transition) 8-bit ±10% 54 60 66 MHz
F
STEADY
Frequency (steady state) ±500 ppm 59.97 60 60.03 MHz
D
START_8BIT
Duty cycle (first transition) 8-bit ±10% 40 50 60 %
D
STEADY
Duty cycle (steady state) ±500 ppm 49.975 50 50.025 %
t
STEADY
Time to reach the steady state frequency and
duty cycle after the first transition
--1.4ms
t
START_DEV
Clock startup time after the
de-assertion of SuspendM
Peripheral - - 5.6
ms
t
START_HOST
Host - - -
t
PREP
PHY preparation time after the first transition
of the input clock
---µs
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