Datasheet

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STM32F745xx STM32F746xx Electrical characteristics
195
SAI characteristics
Unless otherwise specified, the parameters given in Table 78 for SAI are derived from tests
performed under the ambient temperature, f
PCLKx
frequency and VDD supply voltage
conditions summarized in
Table 17, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C=30 pF
• Measurement points are performed at CMOS levels: 0.5V
DD
Refer to Section 5.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (SCK,SD,WS).
Table 78. SAI characteristics
(1)
Symbol Parameter Conditions Min Max Unit
f
MCKL
SAI Main clock output - 256 x 8K 256xFs
(2)
MHz
F
SCK
SAI clock frequency
Master data: 32 bits - 128xFs
MHz
Slave data: 32 bits - 128xFs
D
SCK
SAI clock frequency duty
cycle
Slave receiver 30 70 %
t
v(FS)
FS valid time Master mode 8 22
ns
t
su(FS)
FS setup time Slave mode 2 -
t
h(FS)
FS hold time
Master mode 8 -
Slave mode 0 -
t
su(SD_MR)
Data input setup time
Master receiver 5 -
t
su(SD_SR)
Slave receiver 3 -
t
h(SD_MR)
Data input hold time
Master receiver 0 -
t
h(SD_SR)
Slave receiver 6 -
t
v(SD_ST)
t
h(SD_ST)
Data output valid time
Slave transmitter (after enable
edge)
-15
t
v(SD_MT)
Master transmitter (after enable
edge)
-20
t
h(SD_MT)
Data output hold time
Master transmitter (after enable
edge)
7-
1. Guaranteed by characterization results.
2. 256xFs maximum corresponds to 45 MHz (APB2 xaximum frequency)
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