Datasheet

DocID027590 Rev 4 159/227
STM32F745xx STM32F746xx Electrical characteristics
195
Refer to Section 5.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (CK, SD, WS).
Note: Refer to RM0385 reference manual I2S section for more details on the sampling frequency
(F
S
).
f
MCK
, f
CK
, and D
CK
values reflect only the digital peripheral behavior. The values of these
parameters might be slightly impacted by the source clock precision. D
CK
depends mainly
on the value of ODD bit. The digital contribution leads to a minimum value of
(I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). F
S
maximum value is supported for each mode/condition.
Table 77. I
2
S dynamic characteristics
(1)
Symbol Parameter Conditions Min Max Unit
f
MCK
I2S Main clock output - 256x8K 256xFs
(2)
MHz
f
CK
I2S clock frequency
Master data: 32 bits - 64xFs
MHz
Slave data: 32 bits - 64xFs
D
CK
I2S clock frequency duty cycle Slave receiver 30 70 %
t
v(WS)
WS valid time Master mode - 5
ns
t
h(WS)
WS hold time Master mode 0 -
t
su(WS)
WS setup time
Slave mode 5 -
ns
Slave mode
PCM short pulse mode
(3)
3-
t
h(WS)
WS hold time
Slave mode 0 -
Slave mode
PCM short pulse mode
(3)
2-
t
su(SD_MR)
Data input setup time
Master receiver 5 -
t
su(SD_SR)
Slave receiver 1 -
t
h(SD_MR)
Data input hold time
Master receiver 5 -
t
h(SD_SR)
Slave receiver 1.5 -
t
v(SD_ST)
Data output valid time
Slave transmitter (after enable edge) - 16
t
v(SD_MT)
Master transmitter (after enable edge) - 3.5
t
h(SD_ST)
Data output hold time
Slave transmitter (after enable edge) 5 -
t
h(SD_MT)
Master transmitter (after enable edge) 0 -
1. Guaranteed by characterization results.
2. The maximum value of 256xFs is 45 MHz (APB1 maximum frequency).
3. Measurement done with respect to I2S_CK rising edge.
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