Datasheet

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STM32F745xx STM32F746xx Electrical characteristics
195
5.3.3 Operating conditions at power-up / power-down (regulator ON)
Subject to general operating conditions for T
A
.
Table 20. Operating conditions at power-up / power-down (regulator ON)
5.3.4 Operating conditions at power-up / power-down (regulator OFF)
Subject to general operating conditions for T
A
.
5.3.5 Reset and power control block characteristics
The parameters given in Table 22 are derived from tests performed under ambient
temperature and V
DD
supply voltage conditions summarized in Table 17.
Table 19. VCAP1/VCAP2 operating conditions
(1)
1. When bypassing the voltage regulator, the two 2.2 µF V
CAP
capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
Symbol Parameter Conditions
CEXT Capacitance of external capacitor 2.2 µF
ESR ESR of external capacitor < 2 Ω
Symbol Parameter Min Max Unit
t
VDD
V
DD
rise time rate 20 ∞
µs/V
V
DD
fall time rate 20 ∞
Table 21. Operating conditions at power-up / power-down (regulator OFF)
(1)
1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when V
DD
reach below
1.08 V.
Symbol Parameter Conditions Min Max Unit
t
VDD
V
DD
rise time rate Power-up 20 ∞
µs/V
V
DD
fall time rate Power-down 20 ∞
t
VCAP
V
CAP_1
and V
CAP_2
rise time rate Power-up 20 ∞
V
CAP_1
and V
CAP_2
fall time rate Power-down 20 ∞
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