Datasheet

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This is information on a product in full production.

February 2016 DocID027590 Rev 4 1/227

STM32F745xx

STM32F746xx

ARM

-based Cortex

-M7 32b MCU+FPU, 462DMIPS, up to 1MB Flash/320+16+ 4KB

RAM, USB OTG HS/FS, ethernet, 18 TIMs, 3 ADCs, 25 com itf, cam & LCD

Datasheet - production data

Features

• Core: ARM

32-bit Cortex

-M7 CPU with FPU,

adaptive real-time accelerator (ART

Accelerator™) and L1-cache: 4KB data cache

and 4KB instruction cache, allowing 0-wait

state execution from embedded Flash memory

and external memories, frequency up to

216 MHz, MPU, 462 DMIPS/2.14 DMIPS/MHz

(Dhrystone 2.1), and DSP instructions.

• Memories

– Up to 1MB of Flash memory

– 1024 bytes of OTP memory

– SRAM: 320KB (including 64KB of data

TCM RAM for critical real-time data) +

16KB of instruction TCM RAM (for critical

real-time routines) + 4KB of backup SRAM

(available in the lowest power modes)

– Flexible external memory controller with up

to 32-bit data bus: SRAM, PSRAM,

SDRAM/LPSDR SDRAM, NOR/NAND

memories

• Dual mode Quad-SPI

• LCD parallel interface, 8080/6800 modes

• LCD-TFT controller up to XGA resolution with

dedicated Chrom-ART Accelerator™ for

enhanced graphic content creation (DMA2D)

• Clock, reset and supply management

– 1.7 V to 3.6 V application supply and I/Os

– POR, PDR, PVD and BOR

– Dedicated USB power

– 4-to-26 MHz crystal oscillator

– Internal 16 MHz factory-trimmed RC (1%

accuracy)

– 32 kHz oscillator for RTC with calibration

– Internal 32 kHz RC with calibration

• Low-power

– Sleep, Stop and Standby modes

–V

BAT

supply for RTC, 32×32 bit backup

registers + 4KB backup SRAM

• 3×12-bit, 2.4 MSPS ADC: up to 24 channels

and 7.2 MSPS in triple interleaved mode

• 2×12-bit D/A converters

• Up to 18 timers: up to thirteen 16-bit (1x low-

power 16-bit timer available in Stop mode) and

two 32-bit timers, each with up to 4

IC/OC/PWM or pulse counter and quadrature

(incremental) encoder input. All 15 timers

running up to 216 MHz. 2x watchdogs, SysTick

timer

• General-purpose DMA: 16-stream DMA

controller with FIFOs and burst support

• Debug mode

– SWD & JTAG interfaces

–Cortex

-M7 Trace Macrocell™

• Up to 168 I/O ports with interrupt capability

– Up to 164 fast I/Os up to 108 MHz

– Up to 166 5 V-tolerant I/Os

• Up to 25 communication interfaces

– Up to 4× I

C interfaces (SMBus/PMBus)

– Up to 4 USARTs/4 UARTs (27 Mbit/s,

ISO7816 interface, LIN, IrDA, modem

control)

– Up to 6 SPIs (up to 50 Mbit/s), 3 with

muxed simplex I

S for audio class

accuracy via internal audio PLL or external

clock

– 2 x SAIs (serial audio interface)

– 2 × CANs (2.0B active) and SDMMC

interface

– SPDIFRX interface

– HDMI-CEC

• Advanced connectivity

– USB 2.0 full-speed device/host/OTG

controller with on-chip PHY

– USB 2.0 high-speed/full-speed

device/host/OTG controller with dedicated

DMA, on-chip full-speed PHY and ULPI

– 10/100 Ethernet MAC with dedicated DMA:

supports IEEE 1588v2 hardware, MII/RMII

• 8- to 14-bit parallel camera interface up to

54 Mbyte/s

• True random number generator

• CRC calculation unit

• RTC: subsecond accuracy, hardware calendar

• 96-bit unique ID

Table 1. Device summary

Reference Part number

STM32F745xx

STM32F745IE, STM32F745VE, STM32F745VG,

STM32F745ZE, STM32F745ZG, STM32F745IG

STM32F746xx

STM32F746BE, STM32F746BG, STM32F746IE,

STM32F746IG, STM32F746NE, STM32F746NG,

STM32F746VE, STM32F746VG, STM32F746ZE,

STM32F746ZG

LQFP100 (14x14 mm)

LQFP144 (20x20 mm)

LQFP176 (24x24 mm)

UFBGA176 (10x10 mm)

&"'!

TFBGA216 (13x13 mm)

LQFP208 (28x28 mm)

WLCSP143

(4.5x5.8 mm)

TFBGA100 (8x8 mm)

www.st.com

Downloaded from Arrow.com.

Summary of content (227 pages)

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STM32F745xx STM32F746xx ARM®-based Cortex®-M7 32b MCU+FPU, 462DMIPS, up to 1MB Flash/320+16+ 4KB RAM, USB OTG HS/FS, ethernet, 18 TIMs, 3 ADCs, 25 com itf, cam & LCD Datasheet - production data Features &"'! ® ® • Core: ARM 32-bit Cortex -M7 CPU with FPU, adaptive real-time accelerator (ART Accelerator™) and L1-cache: 4KB data cache and 4KB instruction cache, allowing 0-wait state execution from embedded Flash memory and external memories, frequency up to 216 MHz, MPU, 462 DMIPS/2.
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Contents STM32F745xx STM32F746xx Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.1 2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1 ARM® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 Memory protection unit . . . . . . . .
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STM32F745xx STM32F746xx Contents 2.22.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.22.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.22.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.22.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.22.6 Window watchdog . . . . . . . . . . . . . . . .
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Contents 4/227 Downloaded from Arrow.com. STM32F745xx STM32F746xx 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.1.
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STM32F745xx STM32F746xx 6 7 Contents 5.3.29 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 191 5.3.30 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 192 5.3.31 SD/SDIO MMC card host interface (SDMMC) characteristics . . . . . . . 194 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 6.1 LQFP100, 14 x 14 mm low-profile quad flat package information . . . . . 196 6.
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List of tables STM32F745xx STM32F746xx List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. 6/227 Downloaded from Arrow.com. Device summary . .
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STM32F745xx STM32F746xx Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89.
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List of tables Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. 8/227 Downloaded from Arrow.com. STM32F745xx STM32F746xx Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . .
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STM32F745xx STM32F746xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41.
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List of figures Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86.
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STM32F745xx STM32F746xx List of figures Figure 87. WLCSP143, 0.4 mm pitch wafer level chip scale package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Figure 88. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 205 Figure 89. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Description 1 STM32F745xx STM32F746xx Description The STM32F745xx and STM32F746xx devices are based on the high-performance ARM® Cortex®-M7 32-bit RISC core operating at up to 216 MHz frequency. The Cortex®-M7 core features a single floating point unit (SFPU) precision which supports all ARM® singleprecision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances the application security.
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Downloaded from Arrow.com. Medical equipment, Industrial applications: PLC, inverters, circuit breakers, Printers, and scanners, Alarm systems, video intercom, and HVAC, Home audio appliances, Mobile applications, Internet of Things, Wearable devices: smartwatches.
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/227 Downloaded from Arrow.com. 82 Yes No 114 Yes No DocID027590 Rev 4 LQFP208 Yes 168 No TFBGA216 4. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 2.17.2: Internal reset OFF). 3. 216 MHz maximum frequency for -40°C to + 85°C ambient temperature range (200 MHz maximum frequency for -40°C to + 105°C ambient temperature range).
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STM32F745xx STM32F746xx 1.1 Description Full compatibility throughout the family The STM32F745xx and STM32F746xx devices are fully pin-to-pin, compatible with the STM32F4xxxx devices, allowing the user to try different peripherals, and reaching higher performances (higher frequency) for a greater degree of freedom during the development cycle. Figure 1 give compatible board designs between the STM32F4xx families. Figure 1. Compatible board design for LQFP100 package 3& 9'' 966$ 95() 9''$ 3$ :.
PAGE 16
Description STM32F745xx STM32F746xx Figure 2.
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STM32F745xx STM32F746xx Functional overview 2 Functional overview 2.1 ARM® Cortex®-M7 with FPU The ARM® Cortex®-M7 with FPU processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and a low-power consumption, while delivering an outstanding computational performance and low interrupt latency.
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Functional overview 2.3 STM32F745xx STM32F746xx Embedded Flash memory The STM32F745xx and STM32F746xx devices embed a Flash memory of up to 1 Mbyte available for storing programs and data. 2.4 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size. Among other applications, CRC-based techniques are used to verify the data transmission or storage integrity.
PAGE 19
STM32F745xx STM32F746xx Functional overview , ^ ŚƌŽŵͲ Zd ĐĐĞůĞƌĂƚŽƌ ; D Ϯ Ϳ D Ϯ > Ͳd&dͺD h^ ͺ,^ͺD D ͺWϮ d, ZE dͺD , W y/D .% , ' &DFKH 'W D h^ Kd' > Ͳd&d D Ϯ ƚŚĞƌŶĞƚ ,^ D ͺD DϮ D ͺW/ ZD ŽƌƚĞǆͲDϳ 'W D ϭ D ͺD Dϭ /d D d D Figure 3.
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Functional overview STM32F745xx STM32F746xx Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: 2.
PAGE 21
STM32F745xx STM32F746xx Functional overview effective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 2.9 Quad-SPI memory interface (QUADSPI) All devices embed a Quad-SPI memory interface, which is a specialized communication interface targetting Single, Dual or Quad-SPI Flash memories. It can work in: • Direct mode through registers. • External flash status register polling mode.
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Functional overview 2.12 STM32F745xx STM32F746xx Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 97 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M7 with FPU core.
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STM32F745xx STM32F746xx 2.15 Functional overview Boot modes At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF which includes: • All Flash address space mapped on ITCM or AXIM interface • All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface • The System memory bootloader The boot loader is located in system memory.
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Functional overview STM32F745xx STM32F746xx Figure 4. VDDUSB connected to VDD power supply 9'' 9''B0$; 9'' 9''$ 9''86% 9''B0,1 2SHUDWLQJ PRGH 3RZHU RQ 3RZHU GRZQ WLPH 06 9 Figure 5. VDDUSB connected to external power supply 9''86%B0$; 86% IXQFWLRQDO DUHD 9''86% 9''86%B0,1 86% QRQ IXQFWLRQDO DUHD 9'' 9''$ 86% QRQ IXQFWLRQDO DUHD 2SHUDWLQJ PRGH 3RZHU GRZQ 9''B0,1 3RZHU RQ WLPH 06 9 2.17 Power supply supervisor 2.17.
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STM32F745xx STM32F746xx Functional overview reached, the option byte loading process starts, either to confirm or modify default BOR thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit.
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Functional overview STM32F745xx STM32F746xx Figure 7. PDR_ON control with internal reset OFF 9 '' 3'5 9 WLPH 5HVHW E\ RWKHU VRXUFH WKDQ SRZHU VXSSO\ VXSHUYLVRU 1567 3'5B21 3'5B21 WLPH 06 9 2.18 Voltage regulator The regulator has four operating modes: • • 2.18.1 Regulator ON – Main regulator mode (MR) – Low-power regulator (LPR) – Power-down Regulator OFF Regulator ON On packages embedding the BYPASS_REG pin, the regulator is enabled by holding BYPASS_REG low.
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STM32F745xx STM32F746xx Functional overview consumption. The over-drive mode allows operating at a higher frequency than the normal mode for a given voltage scaling. – In Stop modes The MR can be configured in two ways during Stop mode: MR operates in normal mode (default mode of MR in Stop mode) MR operates in under-drive mode (reduced leakage mode). • LPR is used in the Stop modes: The LP regulator mode is configured by software when entering Stop mode.
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Functional overview STM32F745xx STM32F746xx In regulator OFF mode, the following features are no more supported: • PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power domain which is not reset by the NRST pin. • As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required.
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STM32F745xx STM32F746xx Functional overview Figure 9. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization 9'' 3'5 9 RU 9 9 0LQ 9 9&$3B 9&$3B WLPH 1567 WLPH DL I 1. This figure is valid whatever the internal reset mode (ON or OFF). Figure 10.
PAGE 30
Functional overview 2.18.3 STM32F745xx STM32F746xx Regulator ON/OFF and internal reset ON/OFF availability Table 4. Regulator ON/OFF and internal reset ON/OFF availability Package Regulator ON Regulator OFF Internal reset ON Internal reset OFF LQFP100 LQFP144, LQFP208 TFBGA100, LQFP176, WLCSP143, UFBGA176, TFBGA216 2.
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STM32F745xx STM32F746xx Functional overview The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes. All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes. 2.
PAGE 32
Functional overview 2.21 STM32F745xx STM32F746xx VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation.
PAGE 33
STM32F745xx STM32F746xx Functional overview Table 6.
PAGE 34
Functional overview 2.22.1 STM32F745xx STM32F746xx Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers.
PAGE 35
STM32F745xx STM32F746xx 2.22.3 Functional overview Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. TIM6 and TIM7 support independent DMA request generation. 2.22.4 Low-power timer (LPTIM1) The low-power timer has an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
PAGE 36
Functional overview 2.23 STM32F745xx STM32F746xx Inter-integrated circuit interface (I2C) The device embeds 4 I2C. Refer to Table 7: I2C implementation for the features implementation. The I2C bus interface handles communication between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: • • I2C-bus specification and user manual rev.
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STM32F745xx STM32F746xx 2.24 Functional overview Universal synchronous/asynchronous receiver transmitters (USART) The device embeds USART. Refer to Table 8: USART implementation for the features implementation. The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format.
PAGE 38
Functional overview STM32F745xx STM32F746xx Table 8. USART implementation (continued) features(1) USART1/2/3/6 UART4/5/7/8 Smartcard mode X - Single-wire half-duplex communication X X IrDA SIR ENDEC block X X LIN mode X X Dual clock domain X X Receiver timeout interrupt X X Modbus communication X X Auto baud rate detection X X Driver Enable X X 1. X: supported. 2.
PAGE 39
STM32F745xx STM32F746xx Functional overview SAI1 and SAI2 can be served by the DMA controller 2.27 SPDIFRX Receiver Interface (SPDIFRX) The SPDIFRX peripheral, is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC-61937. These standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up to 5.1).
PAGE 40
Functional overview 2.29 STM32F745xx STM32F746xx Audio and LCD PLL(PLLSAI) An additional PLL dedicated to audio and LCD-TFT is used for SAI1 peripheral in case the PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or 11.2896 MHz) and the audio application requires both sampling frequencies simultaneously. The PLLSAI is also used to generate the LCD-TFT clock. 2.
PAGE 41
STM32F745xx STM32F746xx 2.32 Functional overview Controller area network (bxCAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated for each CAN.
PAGE 42
Functional overview STM32F745xx STM32F746xx The major features are: 2.35 • Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing • Support of the session request protocol (SRP) and host negotiation protocol (HNP) • 8 bidirectional endpoints • 16 host channels with periodic OUT support • Software configurable to OTG1.3 and OTG2.0 modes of operation • USB 2.
PAGE 43
STM32F745xx STM32F746xx 2.38 Functional overview General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions.
PAGE 44
Functional overview STM32F745xx STM32F746xx This dual digital Interface supports the following features: • two DAC converters: one for each output channel • 8-bit or 12-bit monotonic output • left or right data alignment in 12-bit mode • synchronized update capability • noise-wave generation • triangular-wave generation • dual DAC channel independent or simultaneous conversions • DMA capability for each channel • external triggers for conversion • input voltage reference VREF+ Eight DA
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PAGE 46
Pinouts and pin description STM32F745xx STM32F746xx Figure 12.
PAGE 47
STM32F745xx STM32F746xx Pinouts and pin description Figure 13.
PAGE 48
Pinouts and pin description STM32F745xx STM32F746xx 3( 3( 3( 3( 3( 9%$7 3& 3& 3& 3) 3) 3) 3) 3) 3) 9 66 9 '' 3) 3) 3) 3) 3) 3+ 3+ 15 67 3& 3& 3& 3& 9 '' 9 66$ /4)3 9 '' 9 66 9 &$3B 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 9 ''86% 9 66 3* 3* 3* 3* 3* 3* 3* 3' 3' 9 '' 9 66 3' 3' 3' 3' 3' 3' 3% 3% 3% 3% 1.
PAGE 49
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STM32F745xx STM32F746xx Pinouts and pin description Figure 17. STM32F74xIx UFBGA176 ballout ! 0% 0% " 0% # 0% 0% 0" 0" 0' 0' 0" 0% 0% 0" 0" 0" 0' 0' 6"!4 0) 0) 0) 6$$ 0$2?/. 6$$ $ 0# 0) 0) 0) 633 633 % 0# 0& 0) 0) & 0# 633 6$$ 0( 633 633 633 633 ' 0( 633 6$$ 0( 633 633 633 ( 0( 0& 0& 0( 633 633 * .
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Pinouts and pin description STM32F745xx STM32F746xx Figure 18. STM32F74xNx TFBGA216 ballout $ 3( 3( 3( 3* 3( 3( 3% 3% 3% 3% 3' 3& 3$ 3$ 3$ % 3( 3( 3* 3% 3% 3% 3* 3* 3- 3- 3' 3' 3& 3& 3$ & 9%$7 3, 3, 3. 3. 3. 3* 3* 3- 3' 3' 3' 3, 3, 3$ ' 3& 3) 3, 3, 3, 3, 3. 3.
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STM32F745xx STM32F746xx Pinouts and pin description Table 9. Legend/abbreviations used in the pinout table Name Abbreviation Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O TTa 3.
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Pinouts and pin description STM32F745xx STM32F746xx Table 10.
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STM32F745xx STM32F746xx Pinouts and pin description Table 10.
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Pinouts and pin description STM32F745xx STM32F746xx Table 10.
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STM32F745xx STM32F746xx Pinouts and pin description Table 10.
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Pinouts and pin description STM32F745xx STM32F746xx Table 10.
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STM32F745xx STM32F746xx Pinouts and pin description Table 10.
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Pinouts and pin description STM32F745xx STM32F746xx Table 10.
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STM32F745xx STM32F746xx Pinouts and pin description Table 10.
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Pinouts and pin description STM32F745xx STM32F746xx Table 10.
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STM32F745xx STM32F746xx Pinouts and pin description Table 10.
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Pinouts and pin description STM32F745xx STM32F746xx Table 10.
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STM32F745xx STM32F746xx Pinouts and pin description Table 10.
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Pinouts and pin description STM32F745xx STM32F746xx Table 10.
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STM32F745xx STM32F746xx Pinouts and pin description Table 10.
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Pinouts and pin description STM32F745xx STM32F746xx Table 10.
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STM32F745xx STM32F746xx Pinouts and pin description Table 10.
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Pinouts and pin description STM32F745xx STM32F746xx Table 10.
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STM32F745xx STM32F746xx Pinouts and pin description Table 10.
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Pinouts and pin description STM32F745xx STM32F746xx Table 10.
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STM32F745xx STM32F746xx Pinouts and pin description Table 11.
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Pinouts and pin description STM32F745xx STM32F746xx Table 11. FMC pin definition (continued) 74/227 Downloaded from Arrow.com.
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STM32F745xx STM32F746xx Pinouts and pin description Table 11.
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STM32F745xx STM32F746xx 4 Memory mapping Memory mapping The memory map is shown in Figure 19. Figure 19. Memory map [)))) )))) 5HVHUYHG [( [)))) )))) &RUWH[ 0 LQWHUQDO SHULSKHUDOV [( [( ) )))) $+% [ ['))) )))) 5HVHUYHG [ & [ ))) )))) [ %)) $+% 0E\WH %ORFN &RUWH[ 0 ,QWHUQDO SHULSKHUDOV 5HVHUYHG [ [ [ ))) )))) [ )))) [( ['))) )))) 0E\WH %ORFN )0& [' [&))) )))) $+% 0E\
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Memory mapping STM32F745xx STM32F746xx Table 13. STM32F745xx and STM32F746xx register boundary addresses Bus Cortex-M7 AHB3 AHB2 90/227 Downloaded from Arrow.com.
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STM32F745xx STM32F746xx Memory mapping Table 13.
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Memory mapping STM32F745xx STM32F746xx Table 13. STM32F745xx and STM32F746xx register boundary addresses (continued) Bus APB2 92/227 Downloaded from Arrow.com.
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STM32F745xx STM32F746xx Memory mapping Table 13.
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Electrical characteristics 5 STM32F745xx STM32F746xx Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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STM32F745xx STM32F746xx 5.1.6 Electrical characteristics Power supply scheme Figure 22.
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Electrical characteristics 5.1.7 STM32F745xx STM32F746xx Current consumption measurement Figure 23. Current consumption measurement scheme )$$?6"!4 6"!4 )$$ 6$$ 6$$! AI 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 14: Voltage characteristics, Table 15: Current characteristics, and Table 16: Thermal characteristics may cause permanent damage to the device.
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STM32F745xx STM32F746xx Electrical characteristics Table 15. Current characteristics Symbol Ratings Max.
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Electrical characteristics STM32F745xx STM32F746xx 5.3 Operating conditions 5.3.1 General operating conditions Table 17. General operating conditions Symbol Conditions(1) Parameter Power Scale 3 (VOS[1:0] bits in PWR_CR register = 0x01), Regulator ON, over-drive OFF fHCLK Internal AHB clock frequency fPCLK1 Internal APB1 clock frequency fPCLK2 Internal APB2 clock frequency VDD (4) VDDA (5) Analog operating voltage (ADC limited to 1.2 M samples) Analog operating voltage (ADC limited to 2.
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STM32F745xx STM32F746xx Electrical characteristics Table 17. General operating conditions (continued) Symbol Min Typ Max Power Scale 3 ((VOS[1:0] bits in PWR_CR register = 0x01), 144 MHz HCLK max frequency 1.08 1.14 1.20 Power Scale 2 ((VOS[1:0] bits in PWR_CR register = 0x10), 168 MHz HCLK max frequency with over-drive OFF or 180 MHz with over-drive ON 1.20 1.26 1.
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Electrical characteristics STM32F745xx STM32F746xx 6. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and power-down operation. 7. The over-drive mode is not supported when the internal regulator is OFF. 8. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled 9. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax. 10.
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STM32F745xx STM32F746xx Electrical characteristics Table 19. VCAP1/VCAP2 operating conditions(1) Symbol Parameter Conditions CEXT Capacitance of external capacitor 2.2 µF ESR ESR of external capacitor <2Ω 1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be replaced by two 100 nF decoupling capacitors. 5.3.3 Operating conditions at power-up / power-down (regulator ON) Subject to general operating conditions for TA. Table 20.
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Electrical characteristics STM32F745xx STM32F746xx Table 22. reset and power control block characteristics Symbol VPVD Parameter Conditions Programmable voltage detector level selection VPVDhyst(1) PVD hysteresis VPOR/PDR Power-on/power-down reset threshold Min Typ Max Unit PLS[2:0]=000 (rising edge) 2.09 2.14 2.19 V PLS[2:0]=000 (falling edge) 1.98 2.04 2.08 V PLS[2:0]=001 (rising edge) 2.23 2.30 2.37 V PLS[2:0]=001 (falling edge) 2.13 2.19 2.
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STM32F745xx STM32F746xx Electrical characteristics 1. Guaranteed by design. 2. The reset temporization is measured from the power-on (POR reset or wakeup from VBAT) to the instant when first instruction is read by the user application code. 5.3.6 Over-drive switching characteristics When the over-drive mode switches from enabled to disabled or disabled to enabled, the system clock is stalled during the internal voltage set-up. The over-drive switching characteristics are given in Table 23.
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Electrical characteristics STM32F745xx STM32F746xx Typical and maximum current consumption The MCU is placed under the following conditions: • All I/O pins are in input mode with a static value at VDD or VSS (no load). • All peripherals are disabled except if it is explicitly mentioned. • The Flash memory access time is adjusted both to fHCLK frequency and VDD range (see Table 18: Limitations depending on the operating power supply range).
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STM32F745xx STM32F746xx Electrical characteristics 2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. 3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC for the analog part. 4. Guaranteed by test in production. Table 25.
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Electrical characteristics STM32F745xx STM32F746xx Table 26.
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STM32F745xx STM32F746xx Electrical characteristics Table 27.
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Electrical characteristics STM32F745xx STM32F746xx Table 28.
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STM32F745xx STM32F746xx Electrical characteristics Table 29.
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Electrical characteristics STM32F745xx STM32F746xx 2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. Table 31.
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STM32F745xx STM32F746xx Electrical characteristics Table 32. Typical and maximum current consumptions in Standby mode Typ(1) Symbol Parameter Max(2) TA = 25 °C TA = 25 °C Conditions VDD = VDD= VDD = 1.7 V 2.4 V 3.3 V TA = 85 °C TA = 105 °C VDD = 3.3 V Backup SRAM OFF, RTC and LSE OFF 1.7 1.9 2.3 5(3) 15(3) 31(3) Backup SRAM ON, RTC and LSE OFF 2.4 2.6 3.0 6(3) 20(3) 40(3) Backup SRAM OFF, RTC ON and LSE in low drive mode 2.1 2.4 2.
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Electrical characteristics STM32F745xx STM32F746xx Table 33. Typical and maximum current consumptions in VBAT mode Symbol Parameter Typ Max(2) TA =25 °C TA =85 °C TA =105 °C VBAT = VBAT= VBAT= 1.7 V 2.4 V 3.3 V VBAT = 3.6 V Conditions(1) Backup SRAM OFF, RTC and LSE OFF 0.03 0.03 0.04 0.2 0.4 Backup SRAM ON, RTC and LSE OFF 0.74 0.75 0.78 3.0 7.0 Backup SRAM OFF, RTC ON and LSE in low drive mode 0.40 0.52 0.72 2.8 6.5 Backup SRAM OFF, RTC ON and LSE in medium low drive mode 0.
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STM32F745xx STM32F746xx Electrical characteristics Figure 25. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and LSE in low drive mode) ϰ ϯ͘ϱ ϯ ,''B9%$7 X$ ϭ͘ϲϱ s ϭ͘ϳ s Ϯ͘ϱ ϭ͘ϴ s Ϯ Ϯ s Ϯ͘ϰ s ϭ͘ϱ Ϯ͘ϳ s ϯ s ϭ ϯ͘ϯ s ϯ͘ϲ s Ϭ͘ϱ Ϭ Ϭ ϮϬ ϰϬ ϲϬ ϴϬ ϭϬϬ ϭϮϬ dĞŵƉĞƌĂƚƵƌĞ Σ 06 9 Figure 26.
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Electrical characteristics STM32F745xx STM32F746xx Figure 27. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and LSE in medium high drive mode) ϰ͘ϱ ϰ ,''B9%$7 X$ ϯ͘ϱ ϭ͘ϲϱ s ϯ ϭ͘ϳ s Ϯ͘ϱ ϭ͘ϴ s Ϯ s Ϯ Ϯ͘ϰ s Ϯ͘ϳ s ϭ͘ϱ ϯ s ϭ ϯ͘ϯ s ϯ͘ϲ s Ϭ͘ϱ Ϭ Ϭ ϮϬ ϰϬ ϲϬ ϴϬ ϭϬϬ ϭϮϬ dĞŵƉĞƌĂƚƵƌĞ Σ 06 9 Figure 28.
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STM32F745xx STM32F746xx Electrical characteristics Figure 29. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and LSE in high medium drive mode) ϵ ϴ ϳ ϭ͘ϲϱ s ,''B9%$7 X$ ϲ ϭ͘ϳ s ϱ ϭ͘ϴ s Ϯ s ϰ Ϯ͘ϰ s Ϯ͘ϳ s ϯ ϯ s ϯ͘ϯ s Ϯ ϯ͘ϲ s ϭ Ϭ Ϭ ϮϬ ϰϬ ϲϬ dĞŵƉĞƌĂƚƵƌĞ; Σ Ϳ ϴϬ ϭϬϬ ϭϮϬ 06 9 I/O system current consumption The current consumption of the I/O system has two components: static and dynamic.
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Electrical characteristics STM32F745xx STM32F746xx pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DD × f SW × C where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDD is the MCU supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. Table 34.
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STM32F745xx STM32F746xx Electrical characteristics Table 34. Switching output I/O current consumption(1) (continued) I/O toggling Symbol Parameter Conditions frequency (fsw) MHz Typ Typ VDD = 3.3 V VDD = 1.8 V 2 0.3 0.1 8 1.0 0.5 25 3.5 1.6 50 5.9 4.2 60 10.0 4.4 84 19.12 5.8 90 19.6 - 2 0.3 0.2 8 1.3 0.7 25 3.5 2.3 50 10.26 5.19 60 16.53 - CEXT = 22 pF C = CINT + CS + CEXT I/O switching Current IDDIO CEXT = 33 pF C = CINT + CS + CEXT Unit mA 1.
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Electrical characteristics STM32F745xx STM32F746xx Table 35. Peripheral current consumption IDD(Typ)(1) Peripheral AHB1 (up to 216 MHz) Scale 2 Scale 3 GPIOA 2.2 2.1 1.9 GPIOB 2.1 1.8 1.7 GPIOC 2.3 2.0 1.9 GPIOD 2.2 1.9 1.8 GPIOE 2.2 1.9 1.8 GPIOF 2.2 1.9 1.8 GPIOG 2.1 1.8 1.7 GPIOH 2.0 1.7 1.7 GPIOI 2.3 2.0 1.7 GPIOJ 2.2 1.9 1.7 GPIOK 2.0 1.7 1.7 CRC 1.0 0.9 0.8 BKPSRAM 0.8 0.7 0.6 DMA1 2.7 x N + 5.1 2.6 x N + 4.7 2.2 x N + 4 DMA2 2.2 x N + 4.
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STM32F745xx STM32F746xx Electrical characteristics Table 35. Peripheral current consumption (continued) IDD(Typ)(1) Peripheral Scale 2 Scale 3 TIM2 19.8 18.7 16.1 TIM3 16.6 15.1 13.6 TIM4 16.2 15.1 13.3 TIM5 19 17.8 15.8 TIM6 3 2.7 2.5 TIM7 3 2.7 2.5 TIM12 12.4 11.3 10.3 TIM13 6 5.3 5 TIM14 6 5.3 5 LPTIM1 9.4 8.7 8.1 1.8 1.6 1.4 3 2.9 2.8 SPI3/I2S3(3) 3.2 2.9 2.8 SPDIFRX 2.2 2 1.7 USART2 12.8 12 10.8 USART3 15.6 14.2 13.1 UART4 11.8 10.
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Electrical characteristics STM32F745xx STM32F746xx Table 35. Peripheral current consumption (continued) IDD(Typ)(1) Peripheral APB2 (up to 108 MHz) Unit Scale 1 Scale 2 Scale 3 TIM1 25.2 23.9 20.4 TIM8 25.3 24 20.4 USART1 10.3 9.8 8.2 USART6 10.1 9.7 8.1 ADC1(5) 4.5 4.4 3.5 ADC2 (5) 4.5 4.4 3.5 ADC3 (5) 4.5 4.4 3.3 SDMMC1 8.5 7.9 6.7 SPI1/I2S1(3) 3.1 3 2.5 SPI4 3.1 3 2.5 SYSCFG 1.5 1.4 1 TIM9 8.8 8.4 6.9 TIM10 5.6 5.2 4.3 TIM11 5.4 5.2 4.
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STM32F745xx STM32F746xx 5.3.8 Electrical characteristics Wakeup time from low-power modes The wakeup times given in Table 36 are measured starting from the wakeup event trigger up to the first instruction executed by the CPU: • For Stop or Sleep modes: the wakeup event is WFE. • WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes. All timings are derived from tests performed under ambient temperature and VDD=3.3 V. Table 36.
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Electrical characteristics 5.3.9 STM32F745xx STM32F746xx External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 56: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 30.
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STM32F745xx STM32F746xx Electrical characteristics Table 38. Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit - 32.768 1000 kHz 0.7VDD - VDD VSS - 0.
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Electrical characteristics STM32F745xx STM32F746xx Figure 31. Low-speed external clock source AC timing diagram 9/6(+ 9/6(/ WU /6( WI /6( W W: /6( W: /6( 7/6( I/6(BH[W ([WHUQDO FORFN VRXUFH ,/ 26& B,1 670 ) DL High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator.
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STM32F745xx STM32F746xx Electrical characteristics For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 32). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2.
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Electrical characteristics STM32F745xx STM32F746xx Table 40. LSE oscillator characteristics (fLSE = 32.768 kHz) (1) (continued) Symbol Parameter Gm_crit_max Maximum critical crystal gm tSU(2) Conditions Min Typ Max LSEDRV[1:0]=00 Low drive capability - - 0.48 LSEDRV[1:0]=10 Medium low drive capability - - 0.75 LSEDRV[1:0]=01 Medium high drive capability - - 1.7 LSEDRV[1:0]=11 High drive capability - - 2.7 VDD is stabilized - 2 - start-up time Unit µA/V s 1.
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STM32F745xx STM32F746xx 5.3.10 Electrical characteristics Internal clock source characteristics The parameters given in Table 41 and Table 42 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 17. High-speed internal (HSI) RC oscillator Table 41. HSI oscillator characteristics (1) Symbol fHSI Parameter Conditions Min Typ Max Unit Frequency - - 16 - MHz HSI user trimming step(2) - - - 1 % −8 - 4.
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Electrical characteristics STM32F745xx STM32F746xx Low-speed internal (LSI) RC oscillator Table 42. LSI oscillator characteristics (1) Symbol Parameter fLSI(2) tsu(LSI) Frequency Min Typ Max Unit 17 32 47 kHz (3) LSI oscillator startup time - 15 40 µs (3) LSI oscillator power consumption - 0.4 0.6 µA IDD(LSI) 1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified. 2. Guaranteed by characterization results. 3. Guaranteed by design. Figure 35.
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STM32F745xx STM32F746xx Electrical characteristics Table 43.
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Electrical characteristics STM32F745xx STM32F746xx Table 44. PLLI2S characteristics (continued) Symbol Parameter Conditions Min Typ Max RMS - 90 - peak to peak - ±280 - ps Average frequency of 12.288 MHz N = 432, R = 5 on 1000 samples - 90 - ps WS I2S clock jitter Cycle to cycle at 48 KHz on 1000 samples - 400 - ps IDD(PLLI2S)(4) PLLI2S power consumption on VDD VCO freq = 100 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.
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STM32F745xx STM32F746xx Electrical characteristics Table 45. PLLISAI characteristics (continued) Symbol Parameter Conditions Min Typ Max RMS - 90 - peak to peak - ±280 - ps Average frequency of 12.288 MHz N = 432, R = 5 on 1000 samples - 90 - ps FS clock jitter Cycle to cycle at 48 KHz on 1000 samples - 400 - ps IDD(PLLSAI)(4) PLLSAI power consumption on VDD VCO freq = 100 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.
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Electrical characteristics STM32F745xx STM32F746xx Equation 2 Equation 2 allows to calculate the increment step (INCSTEP): INCSTEP = round [ ( ( 2 15 – 1 ) × md × PLLN ) ⁄ ( 100 × 5 × MODEPER ) ] fVCO_OUT must be expressed in MHz.
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STM32F745xx STM32F746xx Electrical characteristics Figure 37. PLL output clock waveforms in down spread mode )UHTXHQF\ 3//B287 ) [PG WPRGH 7LPH [WPRGH DL E 5.3.13 Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. The devices are shipped to customers with the Flash memory erased. Table 47. Flash memory characteristics Symbol IDD Parameter Supply current Conditions Min Typ Max Write / Erase 8-bit mode, VDD = 1.
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Electrical characteristics STM32F745xx STM32F746xx Table 48. Flash memory programming (continued) Symbol Parameter tERASE256KB Sector (256 KB) erase time tME Vprog Mass erase time Programming voltage Conditions Min(1) Typ Max(1) Unit Program/erase parallelism (PSIZE) = x 8 - 2.1 4 Program/erase parallelism (PSIZE) = x 16 - 1.5 2.6 Program/erase parallelism (PSIZE) = x 32 - 1 2 Program/erase parallelism (PSIZE) = x 8 - 8 16 Program/erase parallelism (PSIZE) = x 16 - 5.6 11.
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STM32F745xx STM32F746xx Electrical characteristics Table 50. Flash memory endurance and data retention Value Symbol NEND tRET Parameter Conditions Endurance Data retention TA = –40 to +85 °C (6 suffix versions) TA = –40 to +105 °C (7 suffix versions) 10 1 kcycle(2) at TA = 85 °C 30 1 kcycle (2) 10 kcycles Unit Min(1) at TA = 105 °C 10 (2) 20 at TA = 55 °C kcycles Years 1. Guaranteed by characterization results. 2. Cycling performed over the whole temperature range. 5.3.
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Electrical characteristics STM32F745xx STM32F746xx Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.
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STM32F745xx STM32F746xx 5.3.15 Electrical characteristics Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination.
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Electrical characteristics STM32F745xx STM32F746xx The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of – 5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency deviation). Negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection. The test results are given in Table 55. Table 55.
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STM32F745xx STM32F746xx Electrical characteristics Table 56. I/O static characteristics (continued) Symbol Parameter FT, TTa and NRST I/O input high level voltage(5) VIH BOOT I/O input high level voltage FT, TTa and NRST I/O input hysteresis VHYS BOOT I/O input hysteresis RPD CIO(8) Weak pulldown equivalent resistor(7) Max 1.7 V≤VDD≤3.6 V 1.75 V≤VDD ≤3.6 V, – 40 °C≤TA ≤105 °C 1.7 V≤VDD ≤3.6 V, 0 °C≤TA ≤105 °C 0.45VDD+0.3 0.7VDD(2) - - 0.17VDD+0.7(1) - - 10%VDD(3) - - 1.7 V≤VDD≤3.6 V 1.
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Electrical characteristics STM32F745xx STM32F746xx 7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the series resistance is minimum (~10% order). 8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results. All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters.
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STM32F745xx STM32F746xx Electrical characteristics Output voltage levels Unless otherwise specified, the parameters given in Table 57 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 17. All I/Os are CMOS and TTL compliant. Table 57. Output voltage characteristics Symbol Parameter Conditions Min Max - 0.4 VDD − 0.4 - VDD − 0.4 - Output low level voltage for an I/O pin TTL port(2) IIO =+8mA 2.7 V ≤VDD ≤3.6 V - 0.
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Electrical characteristics STM32F745xx STM32F746xx Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 39 and Table 58, respectively. Unless otherwise specified, the parameters given in Table 58 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 17. Table 58.
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STM32F745xx STM32F746xx Electrical characteristics Table 58. I/O AC characteristics(1)(2) (continued) OSPEEDRy [1:0] bit value(1) Symbol fmax(IO)out Parameter Conditions Maximum frequency(3) 11 tf(IO)out/ tr(IO)out - tEXTIpw Output high to low level fall time and output low to high level rise time Min Typ Max CL = 30 pF, VDD ≥ 2.7 V - - 100(4) CL = 30 pF, VDD ≥ 1.8 V - - 50 CL = 30 pF, VDD ≥ 1.7 V - - 42.5 CL = 10 pF, VDD≥ 2.7 V - - 180(4) CL = 10 pF, VDD ≥ 1.
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Electrical characteristics 5.3.18 STM32F745xx STM32F746xx NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 56: I/O static characteristics). Unless otherwise specified, the parameters given in Table 59 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 17. Table 59.
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STM32F745xx STM32F746xx 5.3.19 Electrical characteristics TIM timer characteristics The parameters given in Table 60 are guaranteed by design. Refer to Section 5.3.17: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 60.
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Electrical characteristics STM32F745xx STM32F746xx Table 62. ADC characteristics (continued) Symbol fADC fTRIG(2) VAIN RAIN(2) Parameter ADC clock frequency External trigger frequency Conversion voltage range(3) External input impedance RADC(2)(4) Sampling switch resistance CADC(2) Internal sample and hold capacitor Conditions Min Typ Max Unit VDDA = 1.7(1) to 2.4 V 0.6 15 18 MHz VDDA = 2.4 to 3.6 V 0.
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STM32F745xx STM32F746xx Electrical characteristics Table 62. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit IVREF+(2) ADC VREF DC current consumption in conversion mode - - 300 500 µA IVDDA(2) ADC VDDA DC current consumption in conversion mode - - 1.6 1.8 mA 1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.17.2: Internal reset OFF). 2. Guaranteed by characterization results. 3.
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Electrical characteristics STM32F745xx STM32F746xx Table 65. ADC static accuracy at fADC = 36 MHz Symbol Parameter Test conditions ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Typ Max(1) ±4 ±7 ±2 ±3 ±3 ±6 ±2 ±3 ±3 ±6 fADC =36 MHz, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V VDDA −VREF < 1.2 V Unit LSB 1. Guaranteed by characterization results. Table 66.
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STM32F745xx STM32F746xx Electrical characteristics Figure 41. ADC accuracy characteristics ; ,3" )$%!, 6 2%& OR 6 $$! DEPENDING ON PACKAGE = %' %4 %/ %, %$ , 3")$%!, 6 33! 6$$! AI C 1. See also Table 64. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line. 5.
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Electrical characteristics STM32F745xx STM32F746xx General PCB design guidelines Power supply decoupling should be performed as shown in Figure 43 or Figure 44, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 43. Power supply and reference decoupling (VREF+ not connected to VDDA) 670 ) 95() ) Q) 9''$ ) Q) 966$ 95() DL E 1.
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STM32F745xx STM32F746xx 5.3.22 Electrical characteristics Temperature sensor characteristics Table 68. Temperature sensor characteristics Symbol Parameter Min Typ Max Unit VSENSE linearity with temperature - ±1 ±2 °C Average slope - 2.5 - mV/°C Voltage at 25 °C - 0.76 - V tSTART(2) Startup time - 6 10 µs TS_temp(2) ADC sampling time when reading the temperature (1 °C accuracy) 10 - - µs TL(1) Avg_Slope (1) V25(1) 1. Guaranteed by characterization results. 2.
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Electrical characteristics STM32F745xx STM32F746xx Table 71. internal reference voltage (continued) Symbol Parameter TCoeff(2) tSTART (2) Conditions Min Typ Max Unit Temperature coefficient - - 30 50 ppm/°C Startup time - - 6 10 µs 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design. Table 72. Internal reference voltage calibration values Symbol Parameter VREFIN_CAL 5.3.
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STM32F745xx STM32F746xx Electrical characteristics Table 73. DAC characteristics (continued) Symbol Min Typ Max Unit Comments - 280 380 µA With no load, middle code (0x800) on the inputs - 475 625 µA With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs Differential non linearity Difference between two consecutive code-1LSB) - - ±0.5 LSB Given for the DAC in 10-bit configuration. - - ±2 LSB Given for the DAC in 12-bit configuration.
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Electrical characteristics STM32F745xx STM32F746xx Figure 45. 12-bit buffered /non-buffered DAC %XIIHUHG 1RQ EXIIHUHG '$& %XIIHU 5 / '$&B287[ ELW GLJLWDO WR DQDORJ FRQYHUWHU & / AI 6 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 5.3.
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STM32F745xx STM32F746xx Electrical characteristics The 20mA output drive requirement in Fast-mode Plus is not supported. This limits the maximum load Cload supported in Fm+, which is given by these formulas: • Tr(SDA/SCL)=0.8473xRpxCload • Rp(min)= (VDD-VOL(max))/IOL(max) Where Rp is the I2C lines pull-up. Refer to Section 5.3.17: I/O port characteristics for the I2C I/Os characteristics. All I2C SDA and SCL I/Os embed an analog filter.
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Electrical characteristics STM32F745xx STM32F746xx SPI interface characteristics Unless otherwise specified, the parameters given in Table 76 for the SPI interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 5.3.
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STM32F745xx STM32F746xx Electrical characteristics Table 76. SPI dynamic characteristics(1) (continued) Symbol tsu(MI) Parameter Data input setup time tsu(SI) th(MI) Data input hold time th(SI) Conditions Min Typ Max Master mode 5.5 - - Slave mode 4 - - Master mode 4 - - Slave mode 2 - - ta(SO) Data output access time Slave mode 7 - 21 tdis(SO) Data output disable time Slave mode 5 - 12 Slave mode 2.7≤VDD≤3.6V - 6.5 10 Slave mode 1.71≤VDD≤3.6V - 6.
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Electrical characteristics STM32F745xx STM32F746xx Figure 47. SPI timing diagram - slave mode and CPHA = 1 166 LQSXW 6&. ,QSXW W68 166 &3+$ &32/ WF 6&. WK 166 WZ 6&.+ WZ 6&./ &3+$ &32/ WY 62 WD 62 0,62 287 3 87 06 % 2 87 WVX 6, 026, , 1387 WK 62 WU 6&. WI 6&. %, 7 287 WGLV 62 /6% 287 WK 6, % , 7 ,1 0 6% ,1 /6% ,1 DL Figure 48. SPI timing diagram - master mode +LJK 166 LQSXW 6&. 2XWSXW &3+$ &32/ 6&. 2XWSXW WF 6&.
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STM32F745xx STM32F746xx Electrical characteristics Refer to Section 5.3.17: I/O port characteristics for more details on the input/output alternate function characteristics (CK, SD, WS). Table 77.
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Electrical characteristics STM32F745xx STM32F746xx Figure 49. I2S slave timing diagram (Philips protocol)(1) WF &. &. ,QSXW &32/ &32/ WZ &.+ WK :6 WZ &./ :6 LQSXW WY 6'B67 WVX :6 6'WUDQVPLW /6% WUDQVPLW 06% WUDQVPLW WVX 6'B65 /6% UHFHLYH 6'UHFHLYH %LWQ WUDQVPLW WK 6'B67 /6% WUDQVPLW WK 6'B65 06% UHFHLYH %LWQ UHFHLYH /6% UHFHLYH DL E 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 50.
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STM32F745xx STM32F746xx Electrical characteristics SAI characteristics Unless otherwise specified, the parameters given in Table 78 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C=30 pF • Measurement points are performed at CMOS levels: 0.5VDD Refer to Section 5.3.
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Electrical characteristics STM32F745xx STM32F746xx Figure 51. SAI master timing waveforms F3#+ 3!)?3#+?8 TH &3 3!)?&3?8 OUTPUT TV &3 TH 3$?-4 TV 3$?-4 3!)?3$?8 TRANSMIT 3LOT N 3LOT N TSU 3$?-2 TH 3$?-2 3!)?3$?8 RECEIVE 3LOT N -3 6 Figure 52. SAI slave timing waveforms F3#+ 3!)?3#+?8 TW #+(?8 3!)?&3?8 INPUT TW #+,?8 TH &3 TSU &3 TH 3$?34 TV 3$?34 3!)?3$?8 TRANSMIT 3LOT N TSU 3$?32 3!)?3$?8 RECEIVE 3LOT N TH 3$?32 3LOT N -3 6 162/227 Downloaded from Arrow.com.
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STM32F745xx STM32F746xx Electrical characteristics USB OTG full speed (FS) characteristics This interface is present in both the USB OTG HS and USB OTG FS controllers. Table 79. USB OTG full speed startup time Symbol tSTARTUP(1) Parameter Max Unit USB OTG full speed transceiver startup time 1 µs 1. Guaranteed by design. Table 80. USB OTG full speed DC electrical characteristics Symbol Parameter Conditions USB OTG full speed VDDUSB transceiver operating voltage Input levels Min. (1) Typ.
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Electrical characteristics STM32F745xx STM32F746xx Figure 53. USB OTG full speed timings: definition of data signal rise and fall time &URVVRYHU SRLQWV 'LIIHUHQWLDO GDWD OLQHV 9&56 966 WU WI DL Table 81. USB OTG full speed electrical characteristics(1) Driver characteristics Symbol tr tf trfm Parameter Rise time(2) Fall time(2) Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 110 % - 1.3 2.
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STM32F745xx STM32F746xx Electrical characteristics Table 83. USB HS clock timing parameters(1) Symbol Parameter Min Typ Max Unit - fHCLK value to guarantee proper operation of USB HS interface 30 - - MHz FSTART_8BIT Frequency (first transition) 54 60 66 MHz FSTEADY Frequency (steady state) ±500 ppm 59.97 60 60.03 MHz DSTART_8BIT Duty cycle (first transition) 40 50 60 % DSTEADY Duty cycle (steady state) ±500 ppm 49.975 50 50.
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Electrical characteristics STM32F745xx STM32F746xx Table 84. Dynamic characteristics: USB ULPI(1) Symbol Parameter Conditions Min. Typ. Max. tSC Control in (ULPI_DIR, ULPI_NXT) setup time - 3 - - tHC Control in (ULPI_DIR, ULPI_NXT) hold time - 1 - - tSD Data in setup time - 1.5 - - tHD Data in hold time - 0.5 - - 2.7 V < VDD < 3.6 V, CL = 20 pF and OSPEEDRy[1:0] = 11 - 5.5 9 - 5.5 11.5 tDC/tDD Data/control output delay 1.7 V < VDD < 3.
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STM32F745xx STM32F746xx Electrical characteristics Table 85. Dynamics characteristics: Ethernet MAC signals for SMI(1) Symbol Min Typ Max MDC cycle time(2.38 MHz) 400 400 403 Td(MDIO) Write data valid time 10 10.5 12.5 tsu(MDIO) Read data setup time 12.5 - - th(MDIO) Read data hold time 0 - - tMDC Parameter Unit ns 1. Guaranteed by characterization results. Table 86 gives the list of Ethernet MAC signals for the RMII and Figure 56 shows the corresponding timing diagram.
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Electrical characteristics STM32F745xx STM32F746xx Table 87 gives the list of Ethernet MAC signals for MII and Figure 56 shows the corresponding timing diagram. Figure 57. Ethernet MII timing diagram -))?28?#,+ -))?28$; = -))?28?$6 -))?28?%2 TSU 28$ TSU %2 TSU $6 TIH 28$ TIH %2 TIH $6 -))?48?#,+ TD 48%. TD 48$ -))?48?%. -))?48$; = AI Table 87.
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STM32F745xx STM32F746xx 5.3.27 Electrical characteristics FMC characteristics Unless otherwise specified, the parameters given in Table 88 to Table 101 for the FMC interface are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 5.3.
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Electrical characteristics STM32F745xx STM32F746xx Figure 58. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms TW .% &-#?.% TV ./%?.% T W ./% T H .%?./% &-#?./% &-#?.7% TV !?.% &-#?!; = T H !?./% !DDRESS TV ",?.% T H ",?./% &-#?.",; = T H $ATA?.% T SU $ATA?./% TH $ATA?./% T SU $ATA?.% $ATA &-#?$; = T V .!$6?.% TW .!$6 &-#?.!$6 &-#?.7!)4 TH .%?.7!)4 TSU .7!)4?.% -3 6 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. 170/227 Downloaded from Arrow.com.
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STM32F745xx STM32F746xx Electrical characteristics Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) Symbol Min Max 2THCLK− 0.5 2 THCLK+1.5 0 1 2THCLK− 1 2THCLK+ 1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 0.5 th(A_NOE) Address hold time after FMC_NOE high 0 - tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.
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Electrical characteristics STM32F745xx STM32F746xx Figure 59. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms TW .% &-#?.%X &-#?./% TV .7%?.% TW .7% T H .%?.7% &-#?.7% TV !?.% &-#?!; = TH !?.7% !DDRESS TV ",?.% &-#?.",; = TH ",?.7% .", TV $ATA?.% TH $ATA?.7% $ATA &-#?$; = T V .!$6?.% &-#?.!$6 TW .!$6 &-#?.7!)4 TH .%?.7!)4 TSU .7!)4?.% -3 6 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. Table 90.
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STM32F745xx STM32F746xx Electrical characteristics Table 91. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings(1) Symbol Parameter tw(NE) tw(NWE) Min Max FMC_NE low time 8THCLK−0.5 8THCLK+1.5 FMC_NWE low time 6THCLK−0.5 6THCLK+1 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK−1 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK+2 - Unit ns 1. Guaranteed by characterization results. Figure 60. Asynchronous multiplexed PSRAM/NOR read waveforms TW .
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Electrical characteristics STM32F745xx STM32F746xx Table 92. Asynchronous multiplexed PSRAM/NOR read timings(1) Symbol tw(NE) tv(NOE_NE) ttw(NOE) th(NE_NOE) tv(A_NE) tv(NADV_NE) tw(NADV) Parameter Min Max 3THCLK−0.5 3THCLK+1.5 FMC_NEx low to FMC_NOE low 2THCLK−1 2THCLK+0.5 FMC_NOE low time THCLK−0.5 THCLK+0.5 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 0.5 FMC_NEx low to FMC_NADV low 0 0.5 THCLK−0.5 THCLK+1.
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STM32F745xx STM32F746xx Electrical characteristics Figure 61. Asynchronous multiplexed PSRAM/NOR write waveforms TW .% &-#? .%X &-#?./% TV .7%?.% TW .7% T H .%?.7% &-#?.7% TH !?.7% TV !?.% &-#? !; = !DDRESS TV ",?.% TH ",?.7% &-#? .",; = .", T V !?.% &-#? !$; = T V $ATA?.!$6 !DDRESS TH $ATA?.7% $ATA TH !$?.!$6 T V .!$6?.% TW .!$6 &-#?.!$6 &-#?.7!)4 TH .%?.7!)4 TSU .7!)4?.% -3 6 Table 94.
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Electrical characteristics STM32F745xx STM32F746xx 1. Guaranteed by characterization results. Table 95. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1) Symbol tw(NE) tw(NWE) Parameter FMC_NE low time FMC_NWE low time Min Max 9THCLK 9THCLK+1.5 7THCLK–0.5 7THCLK+0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK+2 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK–1 - Unit ns 1. Guaranteed by characterization results.
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STM32F745xx STM32F746xx Electrical characteristics Figure 62. Synchronous multiplexed NOR/PSRAM read timings "53452. TW #,+ TW #,+ &-#?#,+ $ATA LATENCY TD #,+, .%X, &-#?.%X T D #,+, .!$6, TD #,+( .%X( TD #,+, .!$6( &-#?.!$6 TD #,+, !6 TD #,+( !)6 &-#?!; = TD #,+, ./%, TD #,+( ./%( &-#?./% T D #,+, !$6 &-#?!$; = TD #,+, !$)6 TSU !$6 #,+( !$; = TH #,+( !$6 TSU !$6 #,+( $ TSU .7!)46 #,+( &-#?.7!)4 7!)4#&' B 7!)40/, B &-#?.7!)4 7!)4#&' B 7!)40/, B TSU .
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Electrical characteristics STM32F745xx STM32F746xx Table 96. Synchronous multiplexed NOR/PSRAM read timings(1) Symbol tw(CLK) Parameter FMC_CLK period Downloaded from Arrow.com. Max 2THCLK−0.5 - - 2 THCLK+0.5 - td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.
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STM32F745xx STM32F746xx Electrical characteristics Figure 63. Synchronous multiplexed PSRAM write timings "53452. TW #,+ TW #,+ &-#?#,+ $ATA LATENCY TD #,+, .%X, TD #,+( .%X( &-#?.%X TD #,+, .!$6, TD #,+, .!$6( &-#?.!$6 TD #,+( !)6 TD #,+, !6 &-#?!; = TD #,+( .7%( TD #,+, .7%, &-#?.7% TD #,+, !$)6 TD #,+, !$6 &-#?!$; = TD #,+, $ATA TD #,+, $ATA !$; = $ $ &-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( TH #,+( .7!)46 TD #,+( .",( &-#?.
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Electrical characteristics STM32F745xx STM32F746xx Table 97. Synchronous multiplexed PSRAM write timings(1) Symbol Min Max 2THCLK−0.5 - - 1.5 THCLK+0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - - 2 THCLK - - 1.5 THCLK−0.5 - tw(CLK) Parameter FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..
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STM32F745xx STM32F746xx Electrical characteristics Figure 64. Synchronous non-multiplexed NOR/PSRAM read timings TW #,+ TW #,+ &-#?#,+ TD #,+, .%X, TD #,+( .%X( $ATA LATENCY &-#?.%X TD #,+, .!$6, TD #,+, .!$6( &-#?.!$6 TD #,+( !)6 TD #,+, !6 &-#?!; = TD #,+, ./%, TD #,+( ./%( &-#?./% TSU $6 #,+( TH #,+( $6 TSU $6 #,+( &-#?$; = TH #,+( $6 $ TSU .7!)46 #,+( &-#?.7!)4 7!)4#&' B 7!)40/, B $ TH #,+( .7!)46 TSU .7!)46 #,+( &-#?.7!)4 7!)4#&' B 7!)40/, B TSU .
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Electrical characteristics STM32F745xx STM32F746xx 1. Guaranteed by characterization results. Figure 65. Synchronous non-multiplexed PSRAM write timings TW #,+ TW #,+ &-#?#,+ TD #,+, .%X, TD #,+( .%X( $ATA LATENCY &-#?.%X TD #,+, .!$6, TD #,+, .!$6( &-#?.!$6 TD #,+( !)6 TD #,+, !6 &-#?!; = TD #,+, .7%, TD #,+( .7%( &-#?.7% TD #,+, $ATA TD #,+, $ATA $ &-#?$; = $ &-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( TD #,+( .",( TH #,+( .7!)46 &-#?.
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STM32F745xx STM32F746xx Electrical characteristics Table 99. Synchronous non-multiplexed PSRAM write timings(1) Symbol Min Max 2THCLK−1 - - 2.5 THCLK+0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - t(CLK) Parameter FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 2.
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Electrical characteristics STM32F745xx STM32F746xx Figure 66. NAND controller waveforms for read access &-#?.#%X !,% &-#?! #,% &-#?! &-#?.7% TD !,% ./% TH ./% !,% &-#?./% .2% TSU $ ./% TH ./% $ &-#?$; = -3 6 Figure 67. NAND controller waveforms for write access &-#?.#%X !,% &-#?! #,% &-#?! TH .7% !,% TD !,% .7% &-#?.7% &-#?./% .2% TH .7% $ TV .7% $ &-#?$; = -3 6 Figure 68. NAND controller waveforms for common memory read access &-#?.
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STM32F745xx STM32F746xx Electrical characteristics Figure 69. NAND controller waveforms for common memory write access &-#?.#%X !,% &-#?! #,% &-#?! TD !,% ./% TW .7% TH ./% !,% &-#?.7% &-#?. /% TD $ .7% TV .7% $ TH .7% $ &-#?$; = -3 6 Table 100. Switching characteristics for NAND Flash read cycles(1) Symbol tw(N0E) Parameter FMC_NOE low width Min Max 4THCLK−0.
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Electrical characteristics STM32F745xx STM32F746xx SDRAM waveforms and timings • CL = 30 pF on data and address lines. CL = 10 pF on FMC_SDCLK unless otherwise specified. In all timing tables, the THCLK is the HCLK clock period. – For 3.0 V≤VDD≤3.6 V, maximum FMC_SDCLK= 100 MHz at CL=20 pF (on FMC_SDCLK). – For 2.7 V≤VDD≤3.6 V, maximum FMC_SDCLK = 90 MHz at CL=30 pF (on FMC_SDCLK). – For 1.71 V≤VDD<1.9 V, maximum FMC_SDCLK = 70 MHz at CL=10 pF (on FMC_SDCLK). Figure 70.
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STM32F745xx STM32F746xx Electrical characteristics Table 102. SDRAM read timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2THCLK−0.5 2THCLK+0.5 tsu(SDCLKH _Data) Data input setup time 3.5 - th(SDCLKH_Data) Data input hold time 1.5 - td(SDCLKL_Add) Address valid time - 4 td(SDCLKL- SDNE) Chip select valid time - 0.5 th(SDCLKL_SDNE) Chip select hold time 0 - td(SDCLKL_SDNRAS) SDNRAS valid time - 0.
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Electrical characteristics STM32F745xx STM32F746xx Figure 71. SDRAM write access waveforms &-#?3$#,+ TD 3$#,+,?!DD# TH 3$#,+,?!DD2 TD 3$#,+,?!DD2 &-#?!> @ 2OW N #OL #OL #OLI #OLN TH 3$#,+,?!DD# TH 3$#,+,?3.$% TD 3$#,+,?3.$% &-#?3$.%; = TH 3$#,+,?.2!3 TD 3$#,+,?.2!3 &-#?3$.2!3 TD 3$#,+,?.#!3 TH 3$#,+,?.#!3 TD 3$#,+,?.7% TH 3$#,+,?.7% &-#?3$.#!3 &-#?3$.7% TD 3$#,+,?$ATA $ATA &-#?$; = $ATA $ATAI $ATAN TH 3$#,+,?$ATA TD 3$#,+,?.", &-#?.",; = -3 6 Table 104.
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STM32F745xx STM32F746xx Electrical characteristics Table 105. LPSDR SDRAM write timings(1) Symbol Parameter Min Max Unit tw(SDCLK) FMC_SDCLK period 2THCLK−0.5 2THCLK+0.5 td(SDCLKL _Data) Data output valid time - 4 th(SDCLKL _Data) Data output hold time 0 - td(SDCLKL_Add) Address valid time - 3.5 td(SDCLKL-SDNWE) SDNWE valid time - 0.5 th(SDCLKL-SDNWE) SDNWE hold time 0 - td(SDCLKL- SDNE) Chip select valid time - 0.
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Electrical characteristics STM32F745xx STM32F746xx Table 106. Quad-SPI characteristics (continued)in SDR mode(1) (continued) Symbol Parameter Conditions Min Typ Max tw(CKH) tw(CKL) Quad-SPI clock high and low time - t(CK)/2 -1 - t(CK)/2 t(CK)/2 - t(CK)/2+1 ts(IN) Data input setup time 1 - - th(IN) Data input hold time 3 - - tv(OUT) Data output valid time 2.7 V
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STM32F745xx STM32F746xx Electrical characteristics Figure 72. Quad-SPI timing diagram - SDR mode WU &. W &. &ORFN WZ &.+ WY 287 WZ &./ WI &. WK 287 'DWD RXWSXW ' ' WV ,1 'DWD LQSXW ' ' WK ,1 ' ' 06Y 9 Figure 73. Quad-SPI timing diagram - DDR mode WU &. &ORFN W &. WYI 287 'DWD RXWSXW WZ &.+ WKU 287 ' WYU 287 ' ' WZ &./ WKI 287 ' WVI ,1 WKI ,1 'DWD LQSXW ' ' WI &. ' ' WVU ,1 WKU ,1 ' ' ' ' 06Y 9 5.3.
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Electrical characteristics STM32F745xx STM32F746xx Figure 74. DCMI timing diagram '&0,B3,;&/. '&0,B3,;&/. WK +6<1& WVX +6<1& '&0,B+6<1& WK +6<1& WVX 96<1& '&0,B96<1& WVX '$7$ WK '$7$ '$7$> @ 06 9 5.3.
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STM32F745xx STM32F746xx Electrical characteristics Figure 75. LCD-TFT horizontal timing diagram W&/. /&'B&/. /&'B96<1& WY +6<1& WY +6<1& /&'B+6<1& WK '( WY '( /&'B'( WY '$7$ /&'B5> @ /&'B*> @ /&'B%> @ 1JYFM 1JYFM 1JYFM / WK '$7$ +6<1& +RUL]RQWDO ZLGWK EDFN SRUFK $FWLYH ZLGWK +RUL]RQWDO EDFN SRUFK 2QH OLQH 06 9 Figure 76. LCD-TFT vertical timing diagram W&/. /&'B&/.
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Electrical characteristics 5.3.31 STM32F745xx STM32F746xx SD/SDIO MMC card host interface (SDMMC) characteristics Unless otherwise specified, the parameters given in Table 110 for the SDIO/MMC interface are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.
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STM32F745xx STM32F746xx Electrical characteristics Table 110. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V(1) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode - 0 - 50 MHz - SDMMC_CK/fPCLK2 frequency ratio - - - 8/3 - tW(CKL) Clock low time fpp =50 MHz 9.5 10.5 - tW(CKH) Clock high time fpp =50 MHz 8.5 9.5 - ns CMD, D inputs (referenced to CK) in MMC and SD HS mode tISU Input setup time HS fpp =50 MHz 2.
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Package information 6 STM32F745xx STM32F746xx Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 6.1 LQFP100, 14 x 14 mm low-profile quad flat package information Figure 79.
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STM32F745xx STM32F746xx Package information Table 112. LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.
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Package information STM32F745xx STM32F746xx Figure 80. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package recommended footprint AI C 1. Dimensions are expressed in millimeters. Marking of engineering samples The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 81. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package top view example 3URGXFW LGHQWLILFDWLRQ 45.
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STM32F745xx STM32F746xx 6.2 Package information TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package information GGG & Figure 82. TFBGA100, 8 × 8 × 0.8 mm thin fine-pitch ball grid array package outline 6($7,1* 3/$1( % $ EDOO LQGH[ $ EDOO DUHD LGHQWLILHU ' H $ $ $ & ' ) ( ( * $ % & ' ( ) * + . H $ E %$//6 HHH & $ % III & $ 4B0(B9 1. Drawing is not to scale. Table 113. TFBGA100, 8 x 8 × 0.
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Package information STM32F745xx STM32F746xx Table 113. TFBGA100, 8 x 8 × 0.8 mm thin fine-pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max D 7.850 8.000 8.150 0.3091 0.3150 0.3209 D1 - 7.200 - 0.2835 - E 7.850 8.000 8.150 0.3091 0.3150 0.3209 E1 - 7.200 - - 0.2835 - e - 0.800 - - 0.0315 - F - 0.400 - - 0.0157 - G - 0.400 - - 0.0157 - ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.
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STM32F745xx STM32F746xx Package information Table 114. TFBGA100 recommended PCB design rules (0.8 mm pitch BGA) Dimension Recommended values Pitch 0.8 Dpad 0.400 mm Dsm 0.470 mm typ (depends on the soldermask registration tolerance) Stencil opening 0.400 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.120 mm Marking of engineering samples The following figure gives an example of topside marking orientation versus ball A1 identifier location. Figure 84.
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Package information 6.3 STM32F745xx STM32F746xx WLCSP143, 4.539x 5.849 mm, 0.4 mm pitch wafer level chip scale package information Figure 85. WLCSP143, 4.539x 5.849 mm, 0.4 mm pitch wafer level chip scale package outline $ EDOO ORFDWLRQ H EEE ) * 'HWDLO $ H H H $ $ $ %RWWRP YLHZ %XPS VLGH 6LGH YLHZ ' %XPS $ HHH $ ( E FFF GGG $ RULHQWDWLRQ UHIHUHQFH 7RS YLHZ :DIHU EDFN VLGH = ;< = 6HDWLQJ SODQH 'HWDLO $ 5RWDWHG DDD $ B0(B9 1. Drawing is not to scale. Table 115.
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STM32F745xx STM32F746xx Package information Table 115. WLCSP143, 4.539x 5.849 mm, 0.4 mm pitch wafer level chip scale package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max - 0.380 - - 0.0150 - - 0.025 - - 0.0010 - b(3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 4.504 4.539 4.574 0.1773 0.1787 0.1801 E 5.814 5.849 5.884 0.2289 0.2303 0.2317 e - 0.400 - - 0.0157 - e1 - 4.000 - - 0.1575 - e2 - 4.800 - - 0.
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Package information STM32F745xx STM32F746xx Table 116. WLCSP143 recommended PCB design rules Dimension Recommended values Pitch 0.4 Dpad 0.225 mm Dsm 0.290 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.250 mm Stencil thickness 0.100 mm Marking of engineering samples The following figure gives an example of topside marking orientation versus ball A1 identifier location. Figure 87. WLCSP143, 0.
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STM32F745xx STM32F746xx 6.4 Package information LQFP144, 20 x 20 mm low-profile quad flat package information Figure 88. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline C ! ! ! 3%!4).' 0,!.% # MM CCC # ! '!5'% 0,!.% $ + , $ , $ % % % B 0). )$%.4)&)#!4)/. E !?-%?6 1. Drawing is not to scale. Table 117.
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Package information STM32F745xx STM32F746xx Table 117. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.500 - - 0.689 - E 21.800 22.000 22.200 0.8583 0.8661 0.8740 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.
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STM32F745xx STM32F746xx Package information Marking of engineering samples The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 90. LQFP144, 20 x 20mm, 144-pin low-profile quad flat package top view example 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ 3 ' ;(5 : 88 3LQ LGHQWLILHU 'DWH FRGH -3 6 1.
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Package information 6.5 STM32F745xx STM32F746xx LQFP176, 24 x 24 mm low-profile quad flat package information Figure 91. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package outline C ! ! ! # 3EATING PLANE MM GAUGE PLANE K ! , ($ 0). )$%.4)&)#!4)/. , $ :% % (% E :$ B 4?-%?6 1. Drawing is not to scale. Table 118. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol 208/227 Downloaded from Arrow.com.
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STM32F745xx STM32F746xx Package information Table 118. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E 23.900 - 24.100 0.9409 - 0.9488 e - 0.500 - - 0.0197 - HD 25.900 - 26.100 1.0200 - 1.0276 HE 25.900 - 26.100 1.0200 - 1.0276 L 0.450 - 0.750 0.0177 - 0.0295 L1 - 1.000 - - 0.0394 - ZD - 1.250 - - 0.0492 - ZE - 1.250 - - 0.0492 - ccc - - 0.
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Package information STM32F745xx STM32F746xx Figure 92. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package recommended footprint 4?&0?6 1. Dimensions are expressed in millimeters. 210/227 Downloaded from Arrow.com.
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STM32F745xx STM32F746xx Package information Marking of engineering samples The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 93. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package top view example 3URGXFW LGHQWLILFDWLRQ 45. ' *(5 5HYLVLRQ FRGH : 88 'DWH FRGH 3 3LQ LGHQWLILHU 06 9 1.
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Package information 6.6 STM32F745xx STM32F746xx LQFP208, 28 x 28 mm low-profile quad flat package information Figure 94. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package outline 6($7,1* 3/$1( F $ $ $ & FFF & PP $ *$8*( 3/$1( . / ' / ' ' 3,1 ,'(17,),&$7,21 ( ( ( E H 6)@.&@7 1. Drawing is not to scale. Table 119.
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STM32F745xx STM32F746xx Package information Table 119. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 29.800 30.000 30.200 1.1732 1.1811 1.1890 D1 27.800 28.000 28.200 1.0945 1.1024 1.1102 D3 - 25.500 - - 1.0039 - E 29.800 30.000 30.200 1.1732 1.1811 1.1890 E1 27.800 28.000 28.200 1.
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Package information STM32F745xx STM32F746xx Figure 95. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package recommended footprint -3 6 1. Dimensions are expressed in millimeters. 214/227 Downloaded from Arrow.com.
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STM32F745xx STM32F746xx Package information Marking of engineering samples The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 96. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package top view example 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ 5 670 ) %*7 3LQ LGHQWLILHU 'DWH FRGH \HDU ZHHN <:: 06 9 1.
PAGE 216
Package information 6.7 STM32F745xx STM32F746xx UFBGA 176+25, 10 x 10 x 0.65 mm ultra thin-pitch ball grid array package information Figure 97. UFBGA 176+25, 10 × 10 × 0.65 mm ultra thin fine-pitch ball grid array package outline & ^ĞĂƚŝŶŐ ƉůĂŶĞ Ϯ ϰ ĚĚĚ ϭ ď $ EDOO LGHQWLILHU Ğ $ EDOO LQGH[ DUHD $ & & Ğ Z ϭϱ ϭ KddKD s/ t E EDOOV dKW s/ t HHH 0 & $ III 0 & Ϭ ϳͺD ͺsϲ 1. Drawing is not to scale. Table 120. UFBGA 176+25, 10 × 10 × 0.
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STM32F745xx STM32F746xx Package information Figure 98. UFBGA176+25, 10 x 10 x 0.65 mm, ultra fine-pitch ball grid array package recommended footprint 'SDG 'VP Ϭ ϳͺ&Wͺsϭ Table 121. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) Dimension Recommended values Pitch 0.65 mm Dpad 0.300 mm Dsm 0.400 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.300 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.
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Package information STM32F745xx STM32F746xx Marking of engineering samples The following figure gives an example of topside marking orientation versus ball A1 identifier location. Figure 99. UFBGA 176+25, 10 × 10 × 0.6 mm ultra thin fine-pitch ball grid array package top view example 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ 5 670 ) ,*. 'DWH FRGH %DOO $ LQGHQWLILHU < :: 06 9 1.
PAGE 219
STM32F745xx STM32F746xx 6.8 Package information TFBGA216, 13 × 13 × 0.8 mm thin fine-pitch ball grid array package information Figure 100. TFBGA216, 13 × 13 × 0.8 mm thin fine-pitch ball grid array package outline = 6HDWLQJ SODQH GGG = $ $ $ ' H ; $ EDOO $ EDOO LGHQWLILHU LQGH[ DUHD ) ' $ * ( ( H < 5 E EDOOV HHH 0 = < ; III 0 = %27720 9,(: 723 9,(: $ / B0(B9 1. Drawing is not to scale. Table 122. TFBGA216, 13 × 13 × 0.
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Package information STM32F745xx STM32F746xx Table 122. TFBGA216, 13 × 13 × 0.8 mm thin fine-pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max G - 0.900 - - 0.0354 - ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 101. TFBGA216, 13 x 13 x 0.
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STM32F745xx STM32F746xx Package information Marking of engineering samples The following figure gives an example of topside marking orientation versus ball A1 identifier location. Figure 102. TFBGA216, 13 × 13 × 0.8 mm thin fine-pitch ball grid array package top view example 3URGXFW LGHQWLILFDWLRQ 45. ' 5HYLVLRQ FRGH /() 3 %DOO $ LGHQWLILHU 'DWH FRGH : 88 06 9 1.
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Package information 6.9 STM32F745xx STM32F746xx Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: • TA max is the maximum ambient temperature in ° C, • ΘJA is the package junction-to-ambient thermal resistance, in ° C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts.
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STM32F745xx STM32F746xx 7 Part numbering Part numbering Table 125.
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Recommendations when using internal reset OFF Appendix A STM32F745xx STM32F746xx Recommendations when using internal reset OFF When the internal reset is OFF, the following integrated features are no longer supported: A.1 • The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled. • The brownout reset (BOR) circuitry must be disabled. • The embedded programmable voltage detector (PVD) is disabled.
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STM32F745xx STM32F746xx Revision history Revision history Table 127. Document revision history Date Revision 26-May-2015 1 Initial release. 2 Updated Table 53: ESD absolute maximum ratings adding packages. Updated note of Table 32: Typical and maximum current consumptions in Standby mode. Updated Figure 11: STM32F74xVx LQFP100 pinout replacing PB13 and PB14 by PE13 and PE14. Updated Table 51: EMS characteristics replacing 168 MHz by 216 MHz. Updated Section 2.
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Revision history STM32F745xx STM32F746xx Table 127. Document revision history (continued) Date 10-Dec-2015 18-Feb-2016 226/227 Downloaded from Arrow.com. Revision Changes 3 Updated Table 10: STM32F745xx and STM32F746xx pin and ball definition additional functions column: WKUP1, 2, 3, 4, 5, 6 must be respectively PA0, PA2, PC1, PC13, PI8, PI11. Updated Table 62: ADC characteristics adding VREF- negative voltage reference. Update Table 14: Voltage characteristics adding table note 3.
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STM32F745xx STM32F746xx IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.