Datasheet

DocID028479 Rev 1 99/121
STM32F722xx STM32F723xx Memory mapping
100
0x4001 8000- 0x4001 FFFF Reserved
APB2
0x4001 7C00 - 0x4001 7FFF OTG PHY HS Controller
(2)
0x4001 6000- 0x4001 7BFF Reserved
0x4001 5C00 - 0x4001 5FFF SAI2
0x4001 5800 - 0x4001 5BFF SAI1
0x4001 5400 - 0x4001 57FF Reserved
0x4001 5000 - 0x4001 53FF SPI5
0x4001 4C00 - 0x4001 4FFF Reserved
0x4001 4800 - 0x4001 4BFF TIM11
0x4001 4400 - 0x4001 47FF TIM10
0x4001 4000 - 0x4001 43FF TIM9
0x4001 3C00 - 0x4001 3FFF EXTI
0x4001 3800 - 0x4001 3BFF SYSCFG
0x4001 3400 - 0x4001 37FF SPI4
0x4001 3000 - 0x4001 33FF SPI1/I2S1
0x4001 2C00 - 0x4001 2FFF SDMMC1
0x4001 2400 - 0x4001 2BFF Reserved
0x4001 2000 - 0x4001 23FF ADC1 - ADC2 - ADC3
0x4001 1C00- 0x4001 1FFF SDMMC2
0x4001 1800 - 0x4001 1BFF Reserved
0x4001 1400 - 0x4001 17FF USART6
0x4001 1000 - 0x4001 13FF USART1
0x4001 0800 - 0x4001 0FFF Reserved
0x4001 0400 - 0x4001 07FF TIM8
0x4001 0000 - 0x4001 03FF TIM1
Table 13. STM32F722xx and STM32F723xx register boundary
addresses
(1)
(continued)
Bus Boundary address Peripheral
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