Datasheet

STM32F722xx STM32F723xx Pinouts and pin description
DocID028479 Rev 1 75/121
- - 126 B9 154 - B9 C8 126 154 PG11 I/O FT -
SDMMC2_D2, FMC_INT,
EVENTOUT
-
- - 127 B8 155 - B8 B8 127 155 PG12 I/O FT -
LPTIM1_IN1, USART6_RTS,
SDMMC2_D3, FMC_NE4,
EVENTOUT
-
- - 128 A8 156 - A8 D7 128 156 PG13 I/O FT -
TRACED0, LPTIM1_OUT,
USART6_CTS, FMC_A24,
EVENTOUT
-
- - 129 A7 157 - A7 C7 129 157 PG14 I/O FT -
TRACED1, LPTIM1_ETR,
USART6_TX,
QUADSPI_BK2_IO3, FMC_A25,
EVENTOUT
-
- - 130 D7 158 - D7 - 130 158 VSS S - - - -
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
Pin name
(function after
reset)
(1)
Pin type
I/O structure
Notes
Alternate functions
Additional
functions
STM32F722xx STM32F723xx
LQFP64
LQFP100
LQFP144
UFBGA176
LQFP176
WLCSP100
UFBGA176
UFBGA144
LQFP144
LQFP176
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