Datasheet

Functional overview STM32F722xx STM32F723xx
40/121 DocID028479 Rev 1
2.29 Universal serial bus on-the-go full-speed (OTG_FS)
The device embeds an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The major features are:
• Combined Rx and Tx FIFO size of 1.28 Kbytes with dynamic FIFO sizing
• Supports the session request protocol (SRP) and host negotiation protocol (HNP)
• 1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints
• 12 host channels with periodic OUT support
• Software configurable to OTG1.3 and OTG2.0 modes of operation
• USB 2.0 LPM (Link Power Management) support
• Internal FS OTG PHY support
• HNP/SNP/IP inside (no need for any external resistor)
• BCD support
For the OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
2.30 Universal serial bus on-the-go high-speed (OTG_HS)
The device embeds an USB OTG high-speed (up to 480 Mbit/s) device/host/OTG
peripheral. The USB OTG HS supports both full-speed and high-speed operations. It
integrates the transceivers for full-speed operation (12
Mbit/s).
The STM32F722xx devices feature a UTMI low-pin interface (ULPI) for high-speed
operation (480
Mbit/s). When using the USB OTG HS in HS mode, an external PHY device
connected to the ULPI is required.
The STM32F723xx devices feature an integrated PHY HS.
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48
MHz clock that is
generated by a PLL connected to the HSE oscillator.
The major features are:
• Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing
• Supports the session request protocol (SRP) and host negotiation protocol (HNP)
• 8 bidirectional endpoints
• 16 host channels with periodic OUT support
• Software configurable to OTG1.3 and OTG2.0 modes of operation
• USB 2.0 LPM (Link Power Management) support
• For the STM32F722xx devices: External HS or HS OTG operation supporting ULPI in
SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12
signals. It can be clocked using the 60 MHz output.
• For the STM32F723xx devices: Internal HS OTG PHY support.
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