Datasheet

DocID028479 Rev 1 25/121
STM32F722xx STM32F723xx Functional overview
43
Figure 9. Power supply supervisor interconnection with internal reset OFF
The V
DD
specified threshold, below which the device must be maintained under reset, is
1.7
V (see Figure 10).
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no more supported:
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
The brownout reset (BOR) circuitry must be disabled
The embedded programmable voltage detector (PVD) is disabled
V
BAT
functionality is no more available and V
BAT
pin should be connected to V
DD
.
All packages, except for the LQFP100, allow to disable the internal reset through the
PDR_ON signal when connected to V
SS
.
Figure 10. PDR_ON control with internal reset OFF
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