Datasheet

Functional overview STM32F722xx STM32F723xx
18/121 DocID028479 Rev 1
2.6 AXI-AHB bus matrix
The STM32F722xx and STM32F723xx system architecture is based on 2 sub-systems:
• An AXI to multi AHB bridge converting AXI4 protocol to AHB-Lite protocol:
– 3x AXI to 32-bit AHB bridges connected to AHB bus matrix
– 1x AXI to 64-bit AHB bridge connected to the embedded Flash memory
• A multi-AHB Bus-Matrix
– The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, USB
HS) and the slaves (Flash memory, RAM, FMC, Quad-SPI, AHB and APB
peripherals) and ensures a seamless and efficient operation even when several
high-speed peripherals work simultaneously.
Figure 6. STM32F722xx and STM32F723xx AXI-AHB bus matrix architecture
(1)
1. The above figure has large wires for 64-bits bus and thin wires for 32-bits bus.
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