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September 2016 DocID028479 Rev 1 1/121

STM32F722xx

STM32F723xx

ARM

-based Cortex

-M7 32b MCU+FPU, 462DMIPS, up to 512KB

Flash/256+16+ 4KB RAM, USB OTG HS/FS, 18 TIMs, 3 ADCs, 21 com itf

Data brief

Features

• Core: ARM

32-bit Cortex

-M7 CPU with FPU,

adaptive real-time accelerator (ART

Accelerator™) and L1-cache: 8 Kbytes of data

cache and 8 Kbytes of instructio

n cache,

allowing 0-wait state execution from embedded

Flash memory and external memories,

frequency up to 216 MHz, MPU,

462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1)

and DSP instructions.

• Memories

– Up to 512 Kbytes of Flash memory wit

protection mechanisms (read and write

protections, propriety code readout

protection (PCROP))

– 528 bytes of OTP memory

– SRAM: 256 Kbytes (including 64 Kb

ytes of

data TCM RAM for critical real-time data) +

16 Kbytes of instruction TCM RAM (for

critical real-time routines) + 4 Kbytes of

backup SRAM (available in the lowest

power modes)

– Flexible external memory controller with up

to 32-bit dat

a bus: SRAM, PSRAM,

SDRAM/LPSDR SDRAM, NOR/NAND

memories

• Dual mode Quad-SPI

• Clock, reset and supply management

– 1.7 V to 3.6 V application supply and I/Os

– POR, PDR, PVD and BOR

– Dedicated USB power

– 4-to-26 MHz crystal oscillator

– Internal 16 MHz factory-trimmed RC (1

accuracy)

– 32 kHz oscillator for RTC with calibration

– Internal 32 kHz RC with calibration

• Low-power

– Sleep, Stop and Standby modes

–V

BAT

supply for RTC, 32×32 bit backup

registers + 4 Kbytes of backup SRAM

• 3×12-bit, 2.4 MSPS ADC: up to 24 channels

and 7.2 MSPS in triple interleaved mode

• 2×12-bit D/A converters

• Up to 18 timers: up to thirteen 16-bit (1x low-

power 16-bit timer available in Stop mode) and

two 32-bit timers, each with up to 4

IC/OC/PWMs or pulse counter and quadrature

(incremental) encoder inputs. All 15 timers

running up to 216 MHz. 2x watchdogs, SysTick

timer

• General-purpose DMA: 16-stream DMA

controller with FIFOs and burst support

• Debug mode

– SWD & JTAG interfaces

–Cortex

-M7 Trace Macrocell™

• Up to 140 I/O ports with interrupt capability

– Up to 136 fast I/Os up to 108 MHz

– Up to 138 5 V-tolerant I/Os

• Up to 21 communication interfaces

– Up to 3× I

C interfaces (SMBus/PMBus)

– Up to 4 USARTs/4 UARTs (27 Mbit/s,

ISO7816 interface, LIN, IrDA, modem

control)

– Up to 5 SPIs (up to 50 Mbit/s), 3 with

muxed simplex I

Ss for audio class

accuracy via internal audio PLL or external

clock

– 2 x SAIs (serial audio interface)

LQFP64 (10 × 10 mm)

UFBGA144 (7 x 7 mm)

&"'!

UFBGA176 (10 x 10 mm)

LQFP176 (24 x 24 mm)

WLCSP100

(0.4 mm pitch)

LQFP144 (20 × 20 mm)

LQFP100 (14 × 14 mm)

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Summary of content (121 pages)

PAGE 1
STM32F722xx STM32F723xx ARM®-based Cortex®-M7 32b MCU+FPU, 462DMIPS, up to 512KB Flash/256+16+ 4KB RAM, USB OTG HS/FS, 18 TIMs, 3 ADCs, 21 com itf Data brief Features • Core: ARM® 32-bit Cortex®-M7 CPU with FPU, adaptive real-time accelerator (ART Accelerator™) and L1-cache: 8 Kbytes of data cache and 8 Kbytes of instruction cache, allowing 0-wait state execution from embedded Flash memory and external memories, frequency up to 216 MHz, MPU, 462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1) and DSP instructions.
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STM32F722xx STM32F723xx – 1 x CAN (2.0B active) – 2 x SDMMCs • • • • True random number generator CRC calculation unit RTC: subsecond accuracy, hardware calendar 96-bit unique ID • Advanced connectivity – USB 2.0 full-speed device/host/OTG controller with on-chip PHY – USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and on-chip Hi-speed PHY or ULPI depending on the product Table 1.
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STM32F722xx STM32F723xx Contents Contents 1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.2 STM32F723xx versus STM32F722xx LQFP144/LQFP176 packages: . . 14 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1 ARM® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . .
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Contents STM32F722xx STM32F723xx 2.20.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.20.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.20.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.20.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.20.7 SysTick timer . . . . . . . . . . . . . . .
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STM32F722xx STM32F723xx 6 Contents 5.6 UFBGA 176+25, 10 x 10, 0.65 mm ultra thin-pitch ball grid array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 5.7 WLCSP100 - 0.4 mm pitch wafer level chip scale package information .114 5.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of tables STM32F722xx STM32F723xx List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. 6/121 Downloaded from Arrow.com. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F722xx STM32F723xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38.
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List of figures STM32F722xx STM32F723xx package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 8/121 Downloaded from Arrow.com.
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STM32F722xx STM32F723xx 1 Description Description The STM32F722xx and STM32F723xx devices are based on the high-performance ARM® Cortex®-M7 32-bit RISC core operating at up to 216 MHz frequency. The Cortex®-M7 core features a single floating point unit (SFPU) precision which supports ARM® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances the application security.
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Description STM32F722xx STM32F723xx These features make the STM32F722xx and STM32F723xx microcontrollers suitable for a wide range of applications: • Motor drive and application control, • Medical equipment, • Industrial applications: PLC, inverters, circuit breakers, • Printers, and scanners, • Alarm systems, video intercom, and HVAC, • Home audio appliances, • Mobile applications, Internet of Things, • Wearable devices: smartwatches.
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STM32F722xx STM32F723xx Description Table 2. STM32F722xx and STM32F723xx features and peripheral counts (continued) Peripherals STM32F72xRx STM32F72xVx STM32F72xIx 1.7 to 3.6 V(8) Operating voltage Ambient temperatures: –40 to +85 °C /–40 to +105 °C Operating temperatures Package STM32F72xZx Junction temperature: –40 to + 125 °C LQFP64(9) LQFP100(9) WLCSP100(10) LQFP144 UFBGA144(10) UFBGA176 LQFP176 1. For the LQFP100 package, only FMC Bank1 is available.
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Description 1.1 STM32F722xx STM32F723xx Full compatibility throughout the family The STM32F722xx devices are fully pin-to-pin, compatible with the STM32F7x5xx, STM32F7x6xx, STM32F7x7xx devices. The STM32F722xx devices are fully pin-to-pin, compatible with the STM32F4xxxx devices, allowing the user to try different peripherals, and reaching higher performances (higher frequency) for a greater degree of freedom during the development cycle.
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STM32F722xx STM32F723xx Description 3& 3& 3& 3$ 3$ 3& 3& 3& 3$ 3$ Figure 2. Compatible board design for LQFP64 package 9'' 9&$3B 3$ 3$ 3$ 3$ 3$ 966 3$ 3& 3& 3& 3& 3% 3% 3% 3% 670 ) [ 3% QRW DYDLODEOH DQ\PRUH 5HSODFHG E\ 9 &$3B 9'' 9'' 966 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 9'' 966 3% 3% 9&$3B 966 9'' 3% 3% 3% 9&$3B 9''
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Description 1.2 STM32F722xx STM32F723xx STM32F723xx versus STM32F722xx LQFP144/LQFP176 packages: Figure 3.
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STM32F722xx STM32F723xx Description Figure 5. STM32F722xx and STM32F723xx block diagram '3 '0 8/3, &. '> @ ',5 673 1;7 6&/ 6'$ ,17 ,' 9%86 )6 3+< 86% +6 3+< $;,0 ' &DFKH .% $+%3 $+%6 /'2 3// 3// %*5 86% 27* +6 3// '0$ ),)2 /'2 $&&(/ &$&+( )/$6+ .% 51* 65$0 .% 65$0 .
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Functional overview STM32F722xx STM32F723xx 2. Available only on the STM32F723xx devices. 2 Functional overview 2.1 ARM® Cortex®-M7 with FPU The ARM® Cortex®-M7 with FPU processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and low interrupt latency.
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STM32F722xx STM32F723xx 2.3 Functional overview Embedded Flash memory The STM32F722xx and STM32F723xx devices embed a Flash memory of up to 512 Kbytes available for storing programs and data. The flexible protections can be configured thanks to option bytes: • 2.4 Readout protection (RDP) to protect the whole memory.
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Functional overview 2.
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STM32F722xx STM32F723xx 2.7 Functional overview DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB).
PAGE 20
Functional overview 2.
PAGE 21
STM32F722xx STM32F723xx 2.10 Functional overview Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 110 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M7 with FPU core.
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Functional overview 2.13 STM32F722xx STM32F723xx Boot modes At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF which includes: • All Flash address space mapped on ITCM or AXIM interface • All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface • The System memory bootloader The boot loader is located in system memory.
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STM32F722xx STM32F723xx Functional overview than VDD – The VDDUSB rising and falling time rate specifications must be respected – In the operating mode phase, VDDUSB could be lower or higher than VDD: - If the USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX. - The VDDUSB supplies both USB transceiver (USB OTG_HS and USB OTG_FS).
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Functional overview STM32F722xx STM32F723xx On the STM32F7x3xx devices, the USB OTG HS sub-system uses an additional power supply pin: • The VDD12OTGHS pin is the output of PHY HS regulator (1.2V). An external capacitor of 2.2 µF must be connected on the VDD12OTGHS pin. 2.15 Power supply supervisor 2.15.1 Internal reset ON On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other packages, the power supply supervisor is always enabled.
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STM32F722xx STM32F723xx Functional overview Figure 9. Power supply supervisor interconnection with internal reset OFF 9'' ([WHUQDO 9'' SRZHU VXSSO\ VXSHUYLVRU ([W UHVHW FRQWUROOHU DFWLYH ZKHQ 9'' 9 1567 9'' $SSOLFDWLRQ UHVHW VLJQDO 3'5B21 966 06 9 The VDD specified threshold, below which the device must be maintained under reset, is 1.7 V (see Figure 10). A comprehensive set of power-saving mode allows to design low-power applications.
PAGE 26
Functional overview 2.16 STM32F722xx STM32F723xx Voltage regulator The regulator has four operating modes: • • 2.16.1 Regulator ON – Main regulator mode (MR) – Low power regulator (LPR) – Power-down Regulator OFF Regulator ON On packages embedding the BYPASS_REG pin, the regulator is enabled by holding BYPASS_REG low. On all other packages, the regulator is always enabled.
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STM32F722xx STM32F723xx Functional overview Table 3. Voltage regulator configuration mode versus device operating mode(1) Voltage regulator configuration Run mode Sleep mode Stop mode Standby mode Normal mode MR MR MR or LPR - Over-drive mode(2) MR MR - - Under-drive mode - - MR or LPR - Power-down mode - - - Yes 1. ‘-’ means that the corresponding configuration is not available. 2. The over-drive mode is not available when VDD = 1.7 to 2.1 V. 2.16.
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Functional overview STM32F722xx STM32F723xx Figure 11. Regulator OFF 9 ([WHUQDO 9&$3B SRZHU $SSOLFDWLRQ UHVHW VXSSO\ VXSHUYLVRU ([W UHVHW FRQWUROOHU DFWLYH VLJQDO RSWLRQDO ZKHQ 9&$3B 0LQ 9 9'' 3$ 9'' 1567 %<3$66B5(* 9 9&$3B 9&$3B DL 9 The following conditions must be respected: • VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains.
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STM32F722xx STM32F723xx Functional overview Figure 12. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization 9'' 3'5 9 RU 9 9 0LQ 9 9&$3B 9&$3B WLPH 1567 WLPH DL I 1. This figure is valid whatever the internal reset mode (ON or OFF). Figure 13.
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Functional overview 2.16.3 STM32F722xx STM32F723xx Regulator ON/OFF and internal reset ON/OFF availability Table 4. Regulator ON/OFF and internal reset ON/OFF availability Package LQFP64, LQFP100 Regulator ON Regulator OFF Yes Internal reset ON Internal reset OFF Yes No No LQFP144 LQFP176, UFBGA144, UFBGA176 2.
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STM32F722xx STM32F723xx Functional overview All the RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes. 2.18 Low-power modes The devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
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Functional overview 2.19 STM32F722xx STM32F723xx VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. The VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
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STM32F722xx STM32F723xx Functional overview Table 6.
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Functional overview 2.20.1 STM32F722xx STM32F723xx Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers.
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STM32F722xx STM32F723xx 2.20.4 Functional overview Low-power timer (LPTIM1) The low-power timer has an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode. This low-power timer supports the following features: 2.20.
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Functional overview 2.21 STM32F722xx STM32F723xx Inter-integrated circuit interface (I2C) The device embeds 3 I2Cs. Refer to Table 7: I2C implementation for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: • • I2C-bus specification and user manual rev.
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STM32F722xx STM32F723xx 2.22 Functional overview Universal synchronous/asynchronous receiver transmitters (USART) The device embeds USARTs. Refer to Table 8: USART implementation for the features implementation. The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format.
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Functional overview STM32F722xx STM32F723xx Table 8. USART implementation (continued) features(1) USART1/2/3/6 UART4/5/7/8 Smartcard mode X - Single-wire half-duplex communication X X IrDA SIR ENDEC block X X LIN mode X X Dual clock domain X X Receiver timeout interrupt X X Modbus communication X X Auto baud rate detection X X Driver Enable X X 1. X: supported. 2.
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STM32F722xx STM32F723xx Functional overview SAI1 and SAI2 can be served by the DMA controller 2.25 Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows to achieve an error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change without disabling the main PLL (PLL) used for CPU and USB interfaces.
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Functional overview 2.29 STM32F722xx STM32F723xx Universal serial bus on-the-go full-speed (OTG_FS) The device embeds an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator.
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STM32F722xx STM32F723xx 2.30.1 Functional overview • Internal USB DMA • HNP/SNP/IP inside (no need for any external resistor) • For OTG/Host modes, a power switch is needed in case bus-powered devices are connected Universal Serial Bus controller on-the-go High-Speed PHY controller (USBPHYC) only on STM32F723xx devices. The USB HS PHY controller: – 2.
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Functional overview 2.34 STM32F722xx STM32F723xx Temperature sensor The temperature sensor has to generate a voltage that varies linearly with the temperature. The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally connected to the same input channel as VBAT, ADC1_IN18, which is used to convert the sensor output voltage into a digital value. When the temperature sensor and VBAT conversion are enabled at the same time, only VBAT conversion is performed.
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STM32F722xx STM32F723xx 2.37 Functional overview Embedded Trace Macrocell™ The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F722xx and STM32F723xx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using the USB or any other high-speed channel.
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Pinouts and pin description STM32F722xx STM32F723xx Figure 16.
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STM32F722xx STM32F723xx Pinouts and pin description 6$$ 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$3$--# 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 17.
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Pinouts and pin description STM32F722xx STM32F723xx 6$$ 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$3$--# 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 18.
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STM32F722xx STM32F723xx Pinouts and pin description Figure 19.
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Pinouts and pin description STM32F722xx STM32F723xx 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$3$--# 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! 6$$ 633 0) 0) 0) 0) 0) 0) 6 $$ Figure 20.
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STM32F722xx STM32F723xx Pinouts and pin description 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$3$--# 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! 6$$ 633 0) 0) 0) 0) 0) 0) 6 $$ Figure 21.
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Pinouts and pin description STM32F722xx STM32F723xx Figure 22.
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STM32F722xx STM32F723xx Pinouts and pin description Figure 23.
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Pinouts and pin description STM32F722xx STM32F723xx Table 9. Legend/abbreviations used in the pinout table Name Pin name Pin type I/O structure Notes Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O TTa 3.
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2 3 4 5 - - - - LQFP64 1 LQFP100 - LQFP144 DocID028479 Rev 1 5 4 3 2 1 B3 B2 B1 A1 A2 UFBGA176 LQFP176 5 4 3 2 1 WLCSP100 B10 E8 D9 A10 C9 STM32F723xx B3 B2 B1 A1 A2 UFBGA176 STM32F722xx B4 B3 B2 A2 A3 UFBGA144 Downloaded from Arrow.com.
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- 7 8 9 - - - 2 3 4 - - - 6 LQFP64 - LQFP100 1 LQFP144 DocID028479 Rev 1 - - - 9 8 7 - 6 E4 E3 D3 F1 E1 D1 D2 C1 UFBGA176 STM32F722xx LQFP176 13 12 11 10 9 8 7 6 WLCSP100 - - - E10 E9 D10 - C10 STM32F723xx E4 E3 D3 F1 E1 D1 D2 C1 UFBGA176 Downloaded from Arrow.com.
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LQFP100 - - - - - - - - 10 11 - LQFP64 - - - - - - - - - - - LQFP144 DocID028479 Rev 1 18 17 16 15 14 13 12 11 10 - - K2 G3 G2 K3 J3 J2 H2 H3 E2 F3 F2 UFBGA176 LQFP176 24 23 22 21 20 19 18 17 16 15 14 WLCSP100 - F10 F9 - - - - - - - - STM32F723xx K2 G3 G2 K3 J3 J2 H2 H3 E2 F3 F2 UFBGA176 STM32F722xx F3 D3 D2 E4 E3 E2 D4 C4 C3 - - UFBGA144 Downloaded from Arrow.com.
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- - - 12 13 14 - - - 5 6 7 LQFP64 - LQFP100 - LQFP144 DocID028479 Rev 1 25 24 23 22 21 20 19 J1 H1 G1 L1 L2 L3 K1 UFBGA176 STM32F722xx LQFP176 31 30 29 28 27 26 25 WLCSP100 G9 H10 G10 - - - - STM32F723xx J1 H1 G1 L1 L2 L3 K1 UFBGA176 Downloaded from Arrow.com.
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16 17 18 - 19 - 20 10 11 - 12 - 13 15 LQFP64 9 LQFP100 8 LQFP144 DocID028479 Rev 1 32 - 31 30 29 28 27 26 P1 N1 M1 - M5 M4 M3 M2 UFBGA176 LQFP176 38 - 37 36 35 34 33 32 WLCSP100 J9 - K10 J7 F7 J10 H9 F8 STM32F723xx P1 N1 M1 - M5 M4 M3 M2 UFBGA176 STM32F722xx L1 K1 J1 F10 H4 H3 H2 H1 UFBGA144 Downloaded from Arrow.com.
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22 23 24 - 15 16 - 21 LQFP64 14 LQFP100 - LQFP144 DocID028479 Rev 1 - 36 35 34 33 F4 P2 N2 N3 R1 UFBGA176 STM32F722xx LQFP176 43 42 41 40 39 WLCSP100 - H8 J8 G8 K9 STM32F723xx F4 P2 N2 N3 R1 UFBGA176 Downloaded from Arrow.com.
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- - 25 26 - 27 28 29 - 17 18 - 19 20 21 - LQFP64 - LQFP100 - LQFP144 DocID028479 Rev 1 41 40 39 - 38 37 - - - P4 N4 K4 L4 - R2 J4 H4 G4 UFBGA176 LQFP176 51 50 49 48 - 47 46 45 44 WLCSP100 F6 G7 - - K8 H7 - - - STM32F723xx P4 N4 K4 L4 - R2 J4 H4 G4 UFBGA176 STM32F722xx K3 J3 F4 H5 G4 M2 - - - UFBGA144 Downloaded from Arrow.com.
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31 32 33 34 35 24 - 25 26 30 LQFP64 23 LQFP100 22 LQFP144 DocID028479 Rev 1 47 46 45 44 43 42 R4 R5 P5 N5 R3 P3 UFBGA176 STM32F722xx LQFP176 57 56 55 54 53 52 WLCSP100 G5 F5 J6 H6 K7 G6 STM32F723xx R4 R5 P5 N5 R3 P3 UFBGA176 Downloaded from Arrow.com.
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- - - - - - - - - 37 38 - - - - - - - - - - 36 LQFP64 - LQFP100 27 LQFP144 DocID028479 Rev 1 59 58 57 56 55 54 53 52 51 50 49 48 P8 R8 M7 N7 P7 R7 N6 N8 M8 P6 R6 M6 UFBGA176 LQFP176 69 68 67 66 65 64 63 62 61 60 59 58 WLCSP100 H5 J5 - - - - - - - - - K6 STM32F723xx P8 R8 M7 N7 P7 R7 N6 N8 M8 P6 R6 M6 UFBGA176 STM32F722xx L7 M7 J6 K6 L6 M6 K5 G5 - L5 M5 J5 UFBGA144 Downloaded from Arrow.com.
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- - 40 41 42 43 44 45 - - - - - - - 39 LQFP64 - LQFP100 - LQFP144 DocID028479 Rev 1 68 67 66 65 64 63 62 61 60 R11 P11 N11 R10 P10 R9 N9 M9 P9 UFBGA176 STM32F722xx LQFP176 78 77 76 75 74 73 72 71 70 WLCSP100 F4 K4 J4 H4 G4 E4 - - K5 STM32F723xx R11 P11 N11 R10 P10 R9 N9 M9 P9 UFBGA176 Downloaded from Arrow.com.
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LQFP100 46 47 48 49 50 - - - - LQFP64 28 29 30 31 32 - - - - LQFP144 DocID028479 Rev 1 - - - - 72 - 71 70 69 M13 M12 N12 M11 N10 - M10 R13 R12 UFBGA176 LQFP176 86 85 84 83 82 - 81 80 79 WLCSP100 - - - - K2 K3 J3 H3 G3 STM32F723xx M9 M13 M12 N12 M11 N10 - M10 - - - - G7 - H7 R13 M10 R12 UFBGA176 STM32F722xx UFBGA144 Downloaded from Arrow.com.
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- - - - 51 52 - - - - - 33 34 - - - LQFP64 - LQFP100 - LQFP144 DocID028479 Rev 1 - - 74 73 - - - - - - - P13 P12 J12 H12 K12 L12 L13 UFBGA176 STM32F722xx LQFP176 - - 93 92 91 90 89 88 87 WLCSP100 G1 G2 H2 J2 K2 - - - - STM32F723xx - - - - - J14 J15 H10 H11 P13 M12 P12 M11 J12 H12 K12 L12 L13 UFBGA176 Downloaded from Arrow.com.
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DocID028479 Rev 1 - 54 - 55 56 - 36 - - - 57 53 LQFP64 - LQFP100 35 LQFP144 79 78 77 - 76 - 75 N15 P14 P15 - R15 - R14 UFBGA176 LQFP176 98 97 96 - 95 - 94 WLCSP100 - - - H1 - J1 - STM32F723xx N15 P14 P15 R15 - R14 - UFBGA176 STM32F722xx J9 K9 L9 L12 - L11 - UFBGA144 Downloaded from Arrow.com.
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LQFP100 58 59 60 - - 61 62 - LQFP64 - - - - - - - - LQFP144 DocID028479 Rev 1 87 86 85 84 83 82 81 80 99 LQFP176 103 102 L15 L14 106 105 M14 104 J13 - M15 101 N13 100 N14 UFBGA176 STM32F722xx WLCSP100 - E2 F1 - - E3 F2 F3 STM32F723xx L10 H9 F8 G8 L15 L14 J12 K12 M14 K11 J13 - M15 K10 N13 N14 UFBGA176 Downloaded from Arrow.com.
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LQFP100 - - - - - - - - 63 LQFP64 - - - - - - - - 37 LQFP144 DocID028479 Rev 1 96 95 94 93 92 91 90 89 88 112 111 110 109 108 107 LQFP176 H15 H13 115 114 G12 113 H14 J14 J15 K13 K14 K15 UFBGA176 WLCSP100 F10 - H15 G12 H13 C11 - - E1 - - H14 G11 - - G12 K1 J10 J11 K13 H12 K14 K15 - - - - - - - STM32F723xx UFBGA176 STM32F722xx UFBGA144 Downloaded from Arrow.com.
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LQFP100 64 65 66 67 68 69 LQFP64 38 39 40 41 42 43 LQFP144 DocID028479 Rev 1 LQFP176 F15 F14 102 D15 121 120 119 118 G14 117 G15 116 101 E15 100 99 98 97 UFBGA176 STM32F722xx WLCSP100 C2 C3 D3 D1 D2 D4 STM32F723xx E12 E11 F11 D15 D11 E15 D12 F15 F14 G14 G15 F12 UFBGA176 Downloaded from Arrow.com.
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72 73 74 75 - - - 46 - 47 48 - - - 70 LQFP64 45 LQFP100 44 LQFP176 LQFP144 DocID028479 Rev 1 F12 F13 126 125 124 123 - - - 129 128 D13 130 E13 E12 108 G13 127 107 106 105 A15 104 B15 103 C15 122 UFBGA176 WLCSP100 - - - A1 A2 B3 B1 B2 C1 STM32F723xx G9 A12 B12 D13 E13 E12 G13 - - - F9 F12 G10 F13 A15 B15 C15 C12 UFBGA176 STM32F722xx UFBGA144 Downloaded from Arrow.com.
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- - - - - 76 77 - - - - 49 50 - LQFP64 - LQFP100 - LQFP144 DocID028479 Rev 1 110 131 LQFP176 C9 D9 A13 138 137 136 135 C13 134 C14 133 D14 132 E14 109 A14 - - - - - - UFBGA176 STM32F722xx WLCSP100 B4 C4 - - - - - - STM32F723xx A13 A14 C9 D9 C13 C14 D14 E14 UFBGA176 Downloaded from Arrow.com.
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LQFP100 78 79 80 81 82 83 84 LQFP64 51 52 53 - - 54 - LQFP144 DocID028479 Rev 1 B12 A12 B13 B14 142 141 140 139 LQFP176 117 D11 145 116 D12 144 115 C12 143 114 113 112 111 UFBGA176 WLCSP100 C6 E5 A4 B5 D5 C5 A3 STM32F723xx B10 B11 E10 D11 D12 D9 E9 C12 D10 B12 A12 C10 B13 B14 UFBGA176 STM32F722xx UFBGA144 Downloaded from Arrow.com.
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86 - - 87 88 - - - - - - - - 85 LQFP64 - LQFP100 - LQFP176 LQFP144 DocID028479 Rev 1 A11 B11 C8 D8 C11 151 150 149 148 147 125 B10 153 124 C10 152 123 122 121 120 119 118 D10 146 UFBGA176 STM32F722xx WLCSP100 - - E6 D6 - - A5 B6 STM32F723xx B10 C10 A11 B11 C8 D8 C11 D10 UFBGA176 Downloaded from Arrow.com.
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DocID028479 Rev 1 - - - - - - - - LQFP64 - LQFP100 - LQFP144 130 129 128 127 126 D7 A7 A8 B8 B9 UFBGA176 LQFP176 158 157 156 155 154 WLCSP100 - - - - - STM32F723xx D7 A7 A8 B8 B9 UFBGA176 STM32F722xx - C7 D7 B8 C8 UFBGA144 Downloaded from Arrow.com.
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LQFP100 - - 89 90 91 LQFP64 - - 55 56 57 LQFP144 B7 C7 DocID028479 Rev 1 135 134 A6 A9 133 A10 132 131 UFBGA176 STM32F722xx LQFP176 163 162 161 160 159 WLCSP100 C7 B7 A6 - - STM32F723xx A6 A9 A10 B7 C7 UFBGA176 Downloaded from Arrow.com.
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93 94 95 96 59 60 61 62 LQFP64 92 LQFP100 58 LQFP144 DocID028479 Rev 1 140 139 138 137 136 B4 A5 D6 B5 B6 UFBGA176 LQFP176 168 167 166 165 164 WLCSP100 D8 C8 A7 B8 D7 STM32F723xx B4 A5 D6 B5 B6 UFBGA176 STM32F722xx B5 C5 D5 D6 C6 UFBGA144 Downloaded from Arrow.com.
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DocID028479 Rev 1 98 99 - - 63 - 143 - 142 141 LQFP144 - - - - - - 100 144 97 LQFP64 64 LQFP100 - C4 D4 C5 C6 D5 A3 A4 UFBGA176 STM32F722xx LQFP176 174 173 172 171 - 170 169 WLCSP100 - - A9 - A8 B9 E7 STM32F723xx C4 D4 C5 C6 D5 A3 A4 UFBGA176 Downloaded from Arrow.com.
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- - - - - - - - - - - - - - - - - - - - - - - - LQFP64 - LQFP100 - LQFP144 DocID028479 Rev 1 - - - - - - - - - - - - - H6 G10 G9 G8 G7 G6 F10 F9 F8 F7 F6 C2 C3 UFBGA176 LQFP176 - - - - - - - - - - - 176 175 WLCSP100 - - - - - - - - - - - - - STM32F723xx H6 G10 G9 G8 G7 G6 F10 F9 F8 F7 F6 C2 C3 UFBGA176 STM32F722xx - - - - - - - - - - - - - UFBGA144 Downloaded from Arrow.com.
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DocID028479 Rev 1 - - - - - - - - - - - - - - LQFP64 - - - - - - - - - - - - - LQFP144 - - - - - - - - - - - - - - K10 K9 K8 K7 K6 J10 J9 J8 J7 J6 H10 H9 H8 H7 LQFP176 - - - - - - - - - - - - - - - - - - - - - - - - - - - - WLCSP100 STM32F723xx K10 K9 K8 K7 K6 J10 J9 J8 J7 J6 H10 H9 H8 H7 - - - - - - - - - - - - - - 1. Function availability depends on the chosen device.
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Downloaded from Arrow.com. 6. If the device is in regulator OFF/internal reset ON mode (BYPASS_REG pin is set to VDD), then PA0 is used as an internal reset (active low). 5. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1). 4. ULPI signals not available on the STM32F723xx devices. 3. Main function after the first backup domain power-up.
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Pinouts and pin description STM32F722xx STM32F723xx Table 11. FMC pin definition 82/121 Downloaded from Arrow.com.
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STM32F722xx STM32F723xx Pinouts and pin description Table 11.
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Pinouts and pin description STM32F722xx STM32F723xx Table 11. FMC pin definition (continued) 84/121 Downloaded from Arrow.com.
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Memory mapping 4 STM32F722xx STM32F723xx Memory mapping The memory map is shown in Figure 24. Figure 24. Memory map [)))) )))) [( ['))) )))) 5HVHUYHG [( [)))) )))) &RUWH[ 0 LQWHUQDO SHULSKHUDOV [( [( ) )))) $+% [ ['))) )))) 5HVHUYHG [ & [ ))) )))) [ %)) $+% 0E\WH %ORFN &RUWH[ 0 ,QWHUQDO SHULSKHUDOV 5HVHUYHG [ [ [ ))) )))) [ )))) 0E\WH %ORFN )0& [' [&))) )))) $+% 0
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STM32F722xx STM32F723xx Memory mapping Table 13.
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Memory mapping STM32F722xx STM32F723xx Table 13. STM32F722xx and STM32F723xx register boundary addresses(1) (continued) Bus AHB1 98/121 Downloaded from Arrow.com.
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STM32F722xx STM32F723xx Memory mapping Table 13.
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Memory mapping STM32F722xx STM32F723xx Table 13.
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STM32F722xx STM32F723xx 5 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 5.1 LQFP64 – 10 x 10 mm, low-profile quad flat package information Figure 25.
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Package information STM32F722xx STM32F723xx Table 14. LQFP64 – 10 x 10 mm, low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max A2 1.350 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 - 0.20 0.0035 D - 12.00 - - 0.4724 - D1 - 10.00 - - 0.3937 - D3 - 7.50 - - 0.2953 - E - 12.00 - - 0.4724 - E1 - 10.00 - - 0.3937 - E3 - 7.50 - - 0.2953 - e - 0.
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STM32F722xx STM32F723xx 5.2 Package information LQFP100, 14 x 14 mm low-profile quad flat package information Figure 27. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline MM C ! ! ! 3%!4).' 0,!.% # '!5'% 0,!.% $ , $ ! + CCC # , $ % % % B 0). )$%.4)&)#!4)/. E ,?-%?6 1. Drawing is not to scale. Table 15.
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Package information STM32F722xx STM32F723xx Table 15. LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1.
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STM32F722xx STM32F723xx 5.3 Package information LQFP144, 20 x 20 mm low-profile quad flat package information Figure 29. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline C ! ! ! 3%!4).' 0,!.% # MM CCC # $ , $ + ! '!5'% 0,!.% , $ % % % B 0). )$%.4)&)#!4)/. E !?-%?6 1. Drawing is not to scale. Table 16.
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Package information STM32F722xx STM32F723xx Table 16. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.500 - - 0.689 - E 21.800 22.000 22.200 0.8583 0.8661 0.8740 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.
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STM32F722xx STM32F723xx 5.4 Package information LQFP176 24 x 24 mm low-profile quad flat package information Figure 31. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package outline C ! ! ! # 3EATING PLANE MM GAUGE PLANE K ! , ($ 0). )$%.4)&)#!4)/. , $ :% % (% E :$ B 4?-%?6 1. Drawing is not to scale. Table 17. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.
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Package information STM32F722xx STM32F723xx Table 17. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E 23.900 - 24.100 0.9409 - 0.9488 e - 0.500 - - 0.0197 - HD 25.900 - 26.100 1.0200 - 1.0276 HE 25.900 - 26.100 1.0200 - 1.0276 L 0.450 - 0.750 0.0177 - 0.0295 L1 - 1.000 - - 0.0394 - ZD - 1.250 - - 0.0492 - ZE - 1.250 - - 0.0492 - ccc - - 0.
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STM32F722xx STM32F723xx Package information Figure 32. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package recommended footprint 4?&0?6 1. Dimensions are expressed in millimeters. DocID028479 Rev 1 109/121 117 Downloaded from Arrow.com.
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Package information 5.5 STM32F722xx STM32F723xx UFBGA144 package information Figure 33. UFBGA144 - 144-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline = 6HDWLQJ SODQH GGG = $ $ $ $ $ ( H $ EDOO $ EDOO LGHQWLILHU LQGH[ DUHD ) ; ( $ ) ' ' H < 0 %27720 9,(: E EDOOV HHH 0 = < ; III 0 = 723 9,(: $ $6B0(B9 1. Drawing is not to scale. Table 18. UFBGA144 - 144-ball, 7 x 7 mm, 0.
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STM32F722xx STM32F723xx Package information Table 18. UFBGA144 - 144-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 34. UFBGA144 - 144-ball, 7 x 7 mm, 0.
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Package information 5.6 STM32F722xx STM32F723xx UFBGA 176+25, 10 x 10, 0.65 mm ultra thin-pitch ball grid array package information Figure 35. UFBGA 176+25, 10 × 10 × 0.65 mm ultra thin fine-pitch ball grid array package outline & ^ĞĂƚŝŶŐ ƉůĂŶĞ Ϯ ϰ ĚĚĚ ϭ ď $ EDOO LGHQWLILHU Ğ $ EDOO LQGH[ DUHD $ & & Ğ Z ϭϱ ϭ KddKD s/ t E EDOOV dKW s/ t HHH 0 & $ III 0 & Ϭ ϳͺD ͺsϲ 1. Drawing is not to scale. Table 20. UFBGA176+25, 10 × 10 × 0.
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STM32F722xx STM32F723xx Package information Figure 36. UFBGA176+25, 10 x 10 mm x 0.65 mm, ultra fine-pitch ball grid array package recommended footprint 'SDG 'VP Ϭ ϳͺ&Wͺsϭ Table 21. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) Dimension Recommended values Pitch 0.65 mm Dpad 0.300 mm Dsm 0.400 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.300 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.
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Package information 5.7 STM32F722xx STM32F723xx WLCSP100 - 0.4 mm pitch wafer level chip scale package information Figure 37.WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale package outline $ %$// /2&$7,21 $ '(7$,/ $ . %27720 9,(: 6,'( 9,(: )5217 9,(: '(7$,/ $ 527$7(' $ 25,(17$7,21 5()(5(1&( DDD ; 723 9,(: :$)(5 %$&. 6,'( 1. Drawing is not to scale. 114/121 Downloaded from Arrow.com.
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STM32F722xx STM32F723xx Package information Table 22. WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Typ Min Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.17 - - 0.0067 - A2 - 0.38 - - 0.0150 - (2) - 0.025 - - 0.0010 - (3) Øb 0.22 0.25 0.28 - 0.0098 0.0110 D 4.166 4.201 4.236 - 0.1654 0.1668 E 4.628 4.663 4.698 - 0.1836 0.1850 e - 0.4 - - 0.
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Package information STM32F722xx STM32F723xx Figure 38. WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale package recommended footprint 'SDG 'VP :/&63 /B$ 4B)3B9 Table 23. WLCSP100 recommended PCB design rules (0.4 mm pitch) Dimension 116/121 Downloaded from Arrow.com. Recommended values Pitch 0.4 mm Dpad 0.225 mm Dsm 0.290 mm Stencil thickness 0.
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STM32F722xx STM32F723xx 5.8 Package information Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: • TA max is the maximum ambient temperature in ° C, • ΘJA is the package junction-to-ambient thermal resistance, in ° C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts.
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Ordering information 6 STM32F722xx STM32F723xx Ordering information Table 24.
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STM32F722xx STM32F723xx Appendix A Recommendations when using internal reset OFF Recommendations when using internal reset OFF When the internal reset is OFF, the following integrated features are no longer supported: A.1 • The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled. • The brownout reset (BOR) circuitry must be disabled. • The embedded programmable voltage detector (PVD) is disabled.
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Revision history STM32F722xx STM32F723xx Revision history Table 26. Document revision history 120/121 Downloaded from Arrow.com. Date Revision 21-Sep-2016 1 Changes Initial release.
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STM32F722xx STM32F723xx IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.