Datasheet

Functional overview STM32F446xC/E
24/202 DocID027107 Rev 6
Figure 6. Power supply supervisor interconnection with internal reset OFF
The V
DD
specified threshold, below which the device must be maintained under reset, is
1.7
V.
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no more supported:
• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
• The brownout reset (BOR) circuitry must be disabled
• The embedded programmable voltage detector (PVD) is disabled
• V
BAT
functionality is no more available and V
BAT
pin should be connected to V
DD
.
All packages, except for the LQFP100/LQFP64, allow to disable the internal reset through
the PDR_ON signal.
3.17 Voltage regulator
The regulator has four operating modes:
• Regulator ON
– Main regulator mode (MR)
– Low power regulator (LPR)
– Power-down
• Regulator OFF
3.17.1 Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
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