Datasheet

DocID027107 Rev 6 21/202
STM32F446xC/E Functional overview
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3.11 Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 91 maskable interrupt channels plus the 16 interrupt lines of the Cortex
®
-
M4 with FPU core.
• Closely coupled NVIC gives low-latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Allows early processing of interrupts
• Processing of late arriving, higher-priority interrupts
• Support tail chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.12 External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 23 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 114 GPIOs can be connected
to the 16 external interrupt lines.
3.13 Clocks and startup
On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16
MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 °C. The application
can then select as system clock either the RC oscillator or an external 4-26 MHz clock
source. This clock can be monitored for failure. If a failure is detected, the system
automatically switches back to the internal RC oscillator and a software interrupt is
generated (if enabled). This clock source is input to a PLL thus allowing to increase the
frequency up to 180
MHz. Similarly, full interrupt management of the PLL clock entry is
available when necessary (for example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 180
MHz while the maximum frequency of the high-speed APB domains is
90
MHz. The maximum allowed frequency of the low-speed APB domain is 45 MHz.
The devices embed a dedicated PLL (PLLI2S) and PLLSAI which allows to achieve audio
class performance. In this case, the I
2
S master clock can generate all standard sampling
frequencies from 8
kHz to 192 kHz.
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