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Electrical characteristics STM32F446xC/E
170/202 DocID027107 Rev 6
Table 100. SDRAM read timings
(1)(2)
1. CL = 30 pF on data and address lines. CL=15pF on FMC_SDCLK.
2. Guaranteed based on test during characterization.
Symbol Parameter Min Max Unit
t
w(SDCLK)
FMC_SDCLK period 2T
HCLK
-0.5 2T
HCLK
+0.5
ns
t
su(SDCLKH _Data)
Data input setup time 1 -
t
h(SDCLKH_Data)
Data input hold time 4 -
t
d(SDCLKL_Add)
Address valid time - 3
t
d(SDCLKL_ SDNE)
Chip select valid time - 1.5
t
h(SDCLKL_SDNE)
Chip select hold time 0 -
t
d(SDCLKL_SDNRAS)
SDNRAS valid time - 1.5
t
h(SDCLKL_SDNRAS)
SDNRAS hold time 0 -
t
d(SDCLKL_SDNCAS)
SDNCAS valid time - 0.5
t
h(SDCLKL_SDNCAS)
SDNCAS hold time 0 -
Table 101. LPSDR SDRAM read timings
(1)(2)
1. CL = 10 pF.
2. Guaranteed based on test during characterization.
Symbol Parameter Min Max Unit
t
w(SDCLK)
FMC_SDCLK period 2T
HCLK
- 0.5 2T
HCLK
+ 0.5
ns
t
su(SDCLKH _Data)
Data input setup time 1 -
t
h(SDCLKH_Data)
Data input hold time 5 -
t
d(SDCLKL_Add)
Address valid time - 3
t
d(SDCLKL_ SDNE)
Chip select valid time - 3
t
h(SDCLKL_SDNE)
Chip select hold time 0 -
t
d(SDCLKL_SDNRAS)
SDNRAS valid time - 2
t
h(SDCLKL_SDNRAS)
SDNRAS hold time 0 -
t
d(SDCLKL_SDNCAS)
SDNCAS valid time - 2
t
h(SDCLKL_SDNCAS)
SDNCAS hold time 0 -
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