Datasheet

DocID027107 Rev 6 159/202
STM32F446xC/E Electrical characteristics
175
Synchronous waveforms and timings
Figure 54 through Figure 57 represent synchronous waveforms and Table 94 through
Table 97 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
• BurstAccessMode = FMC_BurstAccessMode_Enable;
• MemoryType = FMC_MemoryType_CRAM;
• WriteBurst = FMC_WriteBurst_Enable;
• CLKDivision = 1; (0 is not supported, see the STM32F446 reference manual: RM0390)
• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
Table 92. Asynchronous multiplexed PSRAM/NOR write timings
(1)(2)
1. C
L
= 30 pF.
2. Guaranteed based on test during characterization.
Symbol Parameter Min Max Unit
t
w(NE)
FMC_NE low time 4T
HCLK
- 2 4T
HCLK
+0.5
ns
t
v(NWE_NE)
FMC_NEx low to FMC_NWE low T
HCLK
T
HCLK
+ 0.5
t
w(NWE)
FMC_NWE low time 2T
HCLK
2T
HCLK
+ 0.5
t
h(NE_NWE)
FMC_NWE high to FMC_NE high hold time T
HCLK
-
t
v(A_NE)
FMC_NEx low to FMC_A valid - 0
t
v(NADV_NE)
FMC_NEx low to FMC_NADV low 0.5 1
t
w(NADV)
FMC_NADV low time T
HCLK
– 0.5 T
HCLK
+ 0.5
t
h(AD_NADV)
FMC_AD(adress) valid hold time after
FMC_NADV high)
T
HCLK
– 2 -
t
h(A_NWE)
Address hold time after FMC_NWE high T
HCLK
-
t
h(BL_NWE)
FMC_BL hold time after FMC_NWE high T
HCLK
–2 -
t
v(BL_NE)
FMC_NEx low to FMC_BL valid - 2
t
v(Data_NADV)
FMC_NADV high to Data valid - T
HCLK
+ 1.5
t
h(Data_NWE)
Data hold time after FMC_NWE high T
HCLK
+ 0.5 -
Table 93. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings
(1)(2)
1. C
L
= 30 pF.
2. Guaranteed based on test during characterization.
Symbol Parameter Min Max Unit
t
w(NE)
FMC_NE low time 9T
HCLK
9T
HCLK
+ 0.5
ns
t
w(NWE)
FMC_NWE low time 7T
HCLK
7T
HCLK
+ 2
t
su(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx high 6T
HCLK
+ 1.5 -
t
h(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT
invalid
4T
HCLK
– 1 -
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