Datasheet

Electrical characteristics STM32F446xC/E
130/202 DocID027107 Rev 6
Figure 36. SPI timing diagram - slave mode and CPHA = 0
t
w(SCKH)
SCK high and low time Master mode, SPI presc = 2 T
PCLK
- 1.5 T
PCLK
T
PCLK
+ 1.5
ns
t
w(SCKL)
t
su(NSS)
NSS setup time Slave mode, SPI presc = 2 4T
PCLK
--
t
h(NSS)
NSS hold time Slave mode, SPI presc = 2 2T
PCLK
t
su(MI)
Data input setup time
Master mode 4 - -
t
su(SI)
Slave mode 3 - -
t
h(MI)
Data input hold time
Master mode 4 - -
t
h(SI)
Slave mode 2 - -
t
a(SO
) Data output access time Slave mode 7 - 21
t
dis(SO)
Data output disable time Slave mode 5 - 12
t
v(SO)
Data output valid/hold
time
Slave mode (after enable edge),
2.7V ≤ V
DD
≤ 3.6V
-7.522
Slave mode (after enable edge),
1.7 V ≤ V
DD
≤ 3.6 V
- 7.5 10.5
t
h(SO)
Data output valid/hold
time
Slave mode (after enable edge) 5 - -
t
v(MO)
Data output valid time Master mode (after enable edge) - 1.5 5
t
h(MO)
Data output hold time Master mode (after enable edge) 0 - -
1. Guaranteed based on test during characterization.
2. Maximum frequency in Slave transmitter mode is determined by the sum of t
v(SO)
and t
su(MI)
which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having t
su(MI)
= 0 while Duty(SCK) = 50%.
Table 63. SPI dynamic characteristics
(1)
(continued)
Symbol Parameter Conditions Min Typ Max Unit
DLF
6&.,QSXW
166LQSXW
W
68166
WF6&.
WK166
&3+$ 
&32/ 
&3+$ 
&32/ 
W
Z6&.+
WZ6&./
W962 WK62
WU6&.
WI6&.
WGLV62
WD62
0,62
287387
026,
,1387
06%287 %,7287 /6%287
W
VX6,
WK6,
06%,1
%,7,1 /6%,1
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