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This is information on a product in full production.

September 2016 DocID027107 Rev 6 1/202

STM32F446xC/E

ARM

Cortex

-M4 32b MCU+FPU, 225DMIPS, up to 512kB Flash/128+4KB RAM,

USB OTG HS/FS, 17 TIMs, 3 ADCs, 20 comm. interfaces

Datasheet - production data

Features

• Core: ARM

32-bit Cortex

-M4 CPU with FPU,

Adaptive real-time accelerator (ART

Accelerator™) allowing 0-wait state execution

from Fl ash memory, frequency up to 180 MHz,

MPU, 225 DMIPS/1.25 DMIPS/MHz

(Dhrystone 2.1), and DSP instructions

• Memories

– 512 kB of Flash memory

– 128 KB of SRAM

– Flexible external memory controller with up

to 16-bit data bus:

SRAM,PSRAM,SDRAM/LPSDR SDRAM,

Flash NOR/NAND memories

– Dual mode Quad SPI interface

• LCD parallel interface, 8080/6800 modes

• Clock, reset and supply management

– 1.7 V to 3.6 V application supply and I/Os

– POR, PDR, PVD and BOR

– 4-to-26 MHz crystal oscillator

– Internal 16 MHz factory-trimmed RC (1%

accuracy)

– 32 kHz oscillator for RTC with calibration

– Internal 32 kHz RC with calibration

• Low power

– Sleep, Stop and Standby modes

–V

BAT

supply for RTC, 20×32 bit backup

registers + optional 4 KB backup SRAM

• 3×12-bit, 2.4 MSPS ADC: up to 24 channels

and 7.2 MSPS in triple interleaved mode

• 2×12-bit D/A converters

• General-purpose DMA: 16-stream DMA

controller with FIFOs and burst support

• Up to 17 timers: 2x watchdog, 1x SysTick timer

and up to twelve 16-bit and two 32-bit timers up

to 180 MHz, each with up to 4 IC/OC/PWM or

pulse counter

• Debug mode

– SWD & JTAG interfaces

–Cortex

-M4 Trace Macrocell™

• Up to 114 I/O ports with interrupt capability

– Up to 111 fast I/Os up to 90 MHz

– Up to 112 5 V-tolerant I/Os

• Up to 20 communication interfaces

– SPDIF-Rx

– Up to 4 × I

C interfaces (SMBus/PMBus)

– Up to 4 USARTs/2 UARTs (11.25 Mbit/s,

ISO7816 interface, LIN, IrDA, modem

control)

– Up to 4 SPIs (45 Mbits/s), 3 with muxed I

for audio class accuracy via internal audio

PLL or external clock

– 2 x SAI (serial audio interface)

– 2 × CAN (2.0B Active)

– SDIO interface

– Consumer electronics control (CEC) I/F

• Advanced connectivity

– USB 2.0 full-speed device/host/OTG

controller with on-chip PHY

– USB 2.0 high-speed/full-speed

device/host/OTG controller with dedicated

DMA, on-chip full-speed PHY and ULPI

– Dedicated USB power rail enabling on-chip

PHYs operation throughout the entire MCU

power supply range

• 8- to 14-bit parallel camera interface up to

54 Mbytes/s

• CRC calculation unit

• RTC: subsecond accuracy, hardware calendar

• 96-bit unique ID

Table 1. Device summary

Reference Part number

STM32F446xC/E

STM32F446MC, STM32F446ME,

STM32F446RC, STM32F446RE,

STM32F446VC, STM32F446VE,

STM32F446ZC, STM32F446ZE.

LQFP64 (10 × 10mm)

LQFP100 (14 × 14mm)

LQFP144 (20 x 20 mm)

UFBGA144 (7 x 7 mm)

&"'!

UFBGA144 (10 x 10 mm)

WLCSP 81

www.st.com

Downloaded from Arrow.com.

Summary of content (202 pages)

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STM32F446xC/E ARM® Cortex®-M4 32b MCU+FPU, 225DMIPS, up to 512kB Flash/128+4KB RAM, USB OTG HS/FS, 17 TIMs, 3 ADCs, 20 comm. interfaces Datasheet - production data Features &"'! • Core: ARM® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Fl ash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.
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Contents STM32F446xC/E Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 ARM® Cortex®-M4 with FPU and embedded Flash and SRAM . . . . . . . 17 3.2 Adaptive real-time memory accelerator (ART Accelerator™) .
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STM32F446xC/E Contents 3.21.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.21.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.21.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.21.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.21.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents 4/202 Downloaded from Arrow.com. STM32F446xC/E 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F446xC/E 7 8 Contents Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 7.1 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 7.2 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 7.3 LQFP144 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 7.4 UFBGA144 7 x 7 mm package information . . . . . . . . . . . . . . .
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List of figures STM32F446xC/E List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43.
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STM32F446xC/E Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88.
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List of tables STM32F446xC/E List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. 8/202 Downloaded from Arrow.com. Device summary . .
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STM32F446xC/E Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91.
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List of tables Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. 10/202 Downloaded from Arrow.com. STM32F446xC/E Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F446xC/E 1 Introduction Introduction This document provides the description of the STM32F446xC/E products. The STM32F446xC/E document should be read in conjunction with the STM32F4xx reference manual. For information on the Cortex®-M4 core, please refer to the Cortex®-M4 programming manual (PM0214), available from the www.st.com. DocID027107 Rev 6 11/202 40 Downloaded from Arrow.com.
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Description 2 STM32F446xC/E Description The STM32F446xC/E devices are based on the high-performance ARM® Cortex®-M4 32-bit RISC core operating at a frequency of up to 180 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all ARM® single-precision dataprocessing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.
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STM32F446xC/E Description These features make the STM32F446xC/E microcontrollers suitable for a wide range of applications: • Motor drive and application control • Medical equipment • Industrial applications: PLC, inverters, circuit breakers • Printers, and scanners • Alarm systems, video intercom, and HVAC • Home audio appliances Table 2.
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Description STM32F446xC/E 1. For the LQFP100 package, only FMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. 2. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 3.
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STM32F446xC/E Description Figure 2. Compatible board for LQFP64 package 670 ) [[ 3% 9&$3 9'' 3% 3% 9'' 9&$3 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 9'' 966 3% QRW DYDLODEOH DQ\PRUH 5HSODFHG E\ 9&$3 9'' 966 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 9'' 966 3% 3% 9&$3 966 9''
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Description STM32F446xC/E Figure 3. STM32F446xC/E block diagram '0$ ),)2 ,' 9%86 6WUHDPV *3 '0$ ),)2 &/. &6D &6E '> @ )/$6+ N% 65$0 .% 65$0 .% $+% 0+] 6WUHDPV 325 $+% 0+] ),)2 86% 27* )6 6833/< 683(59,6,21 325 3'5 %25 5HVHW ,QW #9''$ *3,2 3257 ' 86$57 0%SV 3( *3,2 3257 ( 86$57 0%SV 3) *3,2 3257 ) 86$57 0%SV 3* *3,2 3257 * 86$57 0%SV 5(6(7 &/2&.
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STM32F446xC/E Functional overview 3 Functional overview 3.1 ARM® Cortex®-M4 with FPU and embedded Flash and SRAM The ARM® Cortex®-M4 with FPU processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
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Functional overview 3.4 STM32F446xC/E Embedded Flash memory The devices embed a Flash memory of 512KB available for storing programs and data. 3.5 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity.
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STM32F446xC/E Functional overview Figure 4. STM32F446xC/E and Multi-AHB matrix 6 6 6 6 86%B+6B0 86% 27* +6 '0$B3 *3 '0$ '0$B0(0 '0$B0(0 '0$B3, 6 EXV 6 *3 '0$ 6 ,&2'( '&2'( $&&(/ 6 ' EXV , EXV $50 &RUWH[ 0 )ODVK PHPRU\ 65$0 .E\WH 65$0 .E\WH $+% SHULSKHUDOV $3% $+% SHULSKHUDOV $3% )0& H[WHUQDO 0HP&WO 4XDG63, %XV PDWUL[ 6 -3 6 3.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each.
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Functional overview STM32F446xC/E The DMA can be used with the main peripherals: 3.9 • SPI and I2S • I2C • USART • General-purpose, basic and advanced-control timers TIMx • DAC • SDIO • Camera interface (DCMI) • ADC • SAI1/SAI2 • SPDIF Receiver (SPDIFRx) • QuadSPI Flexible memory controller (FMC) All devices embed an FMC. It has seven Chip Select outputs supporting the following modes: SDRAM/LPSDR SDRAM, SRAM, PSRAM, NOR Flash and NAND Flash.
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STM32F446xC/E 3.11 Functional overview Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 91 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M4 with FPU core.
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Functional overview 3.14 STM32F446xC/E Boot modes At startup, boot pins are used to select one out of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory through a serial (UART, I2C, CAN, SPI and USB) communication interface. Refer to application note AN2606 for details. 3.15 Note: Power supply schemes • VDD = 1.7 to 3.
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STM32F446xC/E Functional overview Figure 5. VDDUSB connected to an external independent power supply 9''86%B0$; 86% IXQFWLRQDO DUHD 9''86% 9''86%B0,1 86% QRQ IXQFWLRQDO DUHD 9'' 9''$ 86% QRQ IXQFWLRQDO DUHD 2SHUDWLQJ PRGH 3RZHU GRZQ 9''B0,1 3RZHU RQ WLPH 06 9 3.16 Power supply supervisor 3.16.1 Internal reset ON On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other package, the power supply supervisor is always enabled.
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Functional overview STM32F446xC/E Figure 6. Power supply supervisor interconnection with internal reset OFF s ^dDϯϮ&ϰϰϲǆ ƉƉůŝĐĂƚŝŽŶ ƌĞƐĞƚ ƐŝŐŶĂů ;ŽƉƚŝŽŶĂůͿ s d W ZͺKE s^^ W Z ŶŽƚ ĂĐƚŝǀĞ ͗ ϭ͘ϳǀф s фϯ͘ϲǀ D^ϯϯϴϰϰsϭ The VDD specified threshold, below which the device must be maintained under reset, is 1.7 V. A comprehensive set of power-saving mode allows to design low-power applications.
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STM32F446xC/E Functional overview There are three power modes configured by software when the regulator is ON: • MR mode used in Run/sleep modes or in Stop modes – In Run/Sleep mode The MR mode is used either in the normal mode (default mode) or the over-drive mode (enabled by software). Different voltages scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption.
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Functional overview STM32F446xC/E Since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors. When the regulator is OFF, there is no more internal monitoring on V12. An external power supply supervisor should be used to monitor the V12 of the logic power domain.
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STM32F446xC/E Functional overview Figure 8. Startup in regulator OFF: slow VDD slope power-down reset risen after VCAP_1/VCAP_2 stabilization 9'' 3'5 9 RU 9 9 0LQ 9 9&$3B 9&$3B WLPH 1567 WLPH DL I 1. This figure is valid whatever the internal reset mode (ON or OFF). Figure 9. Startup in regulator OFF mode: fast VDD slope power-down reset risen before VCAP_1/VCAP_2 stabilization 9'' 3'5 9 RU 9 9&$3B 9&$3B 9 0LQ 9 1567 WLPH 3$ DVVHUWHG H[WHUQDOO\ WLPH D
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Functional overview STM32F446xC/E Table 4. Regulator ON/OFF and internal reset ON/OFF availability Package Regulator ON Regulator OFF Yes No LQFP144 UFBGA144 WLCSP81 3.
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STM32F446xC/E 3.19 Functional overview Low-power modes The devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the 1.
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Functional overview Note: STM32F446xC/E When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. When PDR_ON pin is not connected to VDD (Internal Reset OFF), the VBAT functionality is no more available and VBAT pin should be connected to VDD. 30/202 Downloaded from Arrow.com.
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STM32F446xC/E 3.21 Functional overview Timers and watchdogs The devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 6 compares the features of the advanced-control, general-purpose and basic timers. Table 6.
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Functional overview 3.21.1 STM32F446xC/E Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers.
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STM32F446xC/E 3.21.4 Functional overview Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. 3.21.
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Functional overview 3.23 STM32F446xC/E Universal synchronous/asynchronous receiver transmitters (USART) The devices embed four universal synchronous/asynchronous receiver transmitters (USART1, USART2, USART3 and USART6) and four universal asynchronous receiver transmitters (UART4, and UART5). These six interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability.
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STM32F446xC/E Functional overview The SPI interface can be configured to operate in TI mode for communications in master mode and slave mode. 3.25 HDMI (high-definition multimedia interface) consumer electronics control (CEC) The devices embeds a HDMI-CEC controller that provides hardware support of consumer electronics control (CEC) (Appendix supplement 1 to the HDMI standard). This protocol provides high-level control functions between all audiovisual products in an environment.
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Functional overview STM32F446xC/E The SPDIF-RX also offers a signal named spdifrx_frame_sync, which toggles at the S/PDIF sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms. 3.28 Serial Audio interface (SAI) The devices feature two serial audio interfaces (SAI1 and SAI2). Each serial audio interfaces based on two independent audio sub blocks which can operate as transmitter or receiver with their FIFO.
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STM32F446xC/E Functional overview The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. 3.32 Controller area network (bxCAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1 Mbit/s.
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Functional overview STM32F446xC/E The major features are: 3.35 • Combined Rx and Tx FIFO size of 1 Kbit × 35 with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 8 bidirectional endpoints • 16 host channels with periodic OUT support • Internal FS OTG PHY support • External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals.
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STM32F446xC/E Functional overview Additional logic functions embedded in the ADC interface allow: • Simultaneous sample and hold • Interleaved sample and hold The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.
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Functional overview STM32F446xC/E Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 3.
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STM32F446xC/E 4 Pinout and pin description Pinout and pin description 9%$7 3& 3& 26& B,1 3% 3% %227 3% 3% 3% 3% 3% 3' 3& 3& 3& 3$ 3$ /4)3 9'' 966 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 3$ 966 9'' 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3% 9&$3B 966 9'' 3&
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Pinout and pin description STM32F446xC/E 6$$ 633 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 11.
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STM32F446xC/E Pinout and pin description 3( 3( 3( 3( 3( 9%$7 3& 3& 3& 3) 3) 3) 3) 3) 3) 9 66 9 '' 3) 3) 3) 3) 3) 3+ 3+ 15 67 3& 3& 3& 3& 9 '' 9 66$ /4)3 9 '' 9 66 9 &$3B 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 9 ''86% 9 66 3* 3* 3* 3* 3* 3* 3* 3' 3' 9 '' 9 66 3' 3' 3' 3' 3' 3' 3% 3% 3% 3% 9 &$3B 9 '' 3$
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Pinout and pin description STM32F446xC/E Figure 13.
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STM32F446xC/E Pinout and pin description Figure 14.
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Pinout and pin description STM32F446xC/E Table 9. Legend/abbreviations used in the pinout table Name Abbreviation Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O FTf 5V tolerant IO, I2C FM+ option TTa 3.
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STM32F446xC/E Pinout and pin description Table 10.
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Pinout and pin description STM32F446xC/E Table 10.
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STM32F446xC/E Pinout and pin description Table 10.
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Pinout and pin description STM32F446xC/E Table 10.
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STM32F446xC/E Pinout and pin description Table 10.
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Pinout and pin description STM32F446xC/E Table 10.
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STM32F446xC/E Pinout and pin description Table 10.
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Pinout and pin description STM32F446xC/E Table 10.
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STM32F446xC/E Pinout and pin description Table 10.
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Pinout and pin description STM32F446xC/E Table 10.
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STM32F446xC/E Pinout and pin description Table 10.
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Pinout and pin description STM32F446xC/E Table 10. STM32F446xx pin and ball descriptions (continued) LQFP64 LQFP100 WLCSP 81 UFBGA144 LQFP144 Pin name (function after reset) Pin type I/O structure Notes Pin Number Alternate functions 63 99 B7 E6 - VSS S - - - - - - B8 E5 143 PDR_ON S - - - - 64 100 A8 F5 144 VDD S - - - - 1. PA11, PA12, PB14 and PB15 I/Os are supplied by VDDUSB 58/202 Downloaded from Arrow.com.
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/202 Downloaded from Arrow.com. 1. PH1 PH0 - - SYS - - TIM1/2 AF1 - - TIM3/4/5 AF2 - - TIM8/9/ 10/11/ CEC AF3 - - I2C1/2/3 /4/CEC AF4 AF5 - - SPI1/2/3/ 4 The DCMI_VSYNC alternate function on PG9 is only available on silicon revision 3. Port H Port AF0 AF7 AF8 AF9 - - - - - SPI2/3/ SAI/ CAN1/2 USART1/ SPI2/3/4/ USART6/ TIM12/13/ 2/3/UART SAI1 UART4/5/ 14/ 5/SPDIFR SPDIFRX QUADSPI X AF6 Table 11.
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STM32F446xC/E 5 Memory mapping Memory mapping The memory map is shown in Figure 15 Figure 15. Memory map [)))) )))) 5HVHUYHG [( [)))) )))) &RUWH[ 0 LQWHUQDO SHULSKHUDOV [( [( ) )))) $+% [ ['))) )))) 5HVHUYHG [ & [ ))) )))) [ %)) $+% 0E\WH %ORFN &RUWH[ 0 ,QWHUQDO SHULSKHUDOV 5HVHUYHG [ [ [ ))) )))) [ )))) [( ['))) )))) 0E\WH %ORFN )0& [' [&))) )))) $+% 0E\WH %ORFN
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Memory mapping STM32F446xC/E Table 12.
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STM32F446xC/E Memory mapping Table 12.
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Memory mapping STM32F446xC/E Table 12. STM32F446xC/E register boundary addresses(1) (continued) Bus Boundary address - 0x4001 6C00- 0x4001 FFFF 0x4001 6800 - 0x4001 6BFF Peripheral Reserved 0x4001 5C00 - 0x4001 5FFF SAI2 0x4001 6000 - 0x4001 67FF Reserved 0x4001 5800 - 0x4001 5BFF SAI1 0x4001 5400 - 0x4001 57FF 0x4001 5000 - 0x4001 53FF Reserved 0x4001 4C00 - 0x4001 4FFF APB2 70/202 Downloaded from Arrow.com.
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STM32F446xC/E Memory mapping Table 12.
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Electrical characteristics STM32F446xC/E 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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STM32F446xC/E 6.1.6 Electrical characteristics Power supply scheme Figure 18. Power supply scheme 9%$7 9%$7 WR 9 *3,2V ,1 î ) 9'' î Q) î ) 9''86% 9&$3B 9&$3B 966 ,2 /RJLF .HUQHO ORJLF &38 GLJLWDO 5$0 9ROWDJH UHJXODWRU %<3$66B5(* 5HVHW FRQWUROOHU 3'5B21 9'' )ODVK PHPRU\ 27* )6 3+< 9''86% Q) ) 9''$ 95() Q) ) /HYHO VKLIWHU 287 9'' %DFNXS FLUFXLWU\ 26& .
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Electrical characteristics 6.1.7 STM32F446xC/E Current consumption measurement Figure 19. Current consumption measurement scheme ,''B9%$7 9%$7 ,'' 9'' 9''$ 9''86% 06Y 9 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 13: Voltage characteristics, Table 14: Current characteristics, and Table 15: Thermal characteristics may cause permanent damage to the device.
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STM32F446xC/E Electrical characteristics Table 14. Current characteristics Symbol Ratings Max.
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Electrical characteristics STM32F446xC/E 6.3 Operating conditions 6.3.1 General operating conditions Table 16. General operating conditions Symbol Parameter Conditions(1) Power Scale 3 (VOS[1:0] bits in PWR_CR register = 0x01), Regulator ON, over-drive OFF fHCLK Internal AHB clock frequency fPCLK1 Internal APB1 clock frequency fPCLK2 Internal APB2 clock frequency 76/202 Downloaded from Arrow.com.
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STM32F446xC/E Electrical characteristics Table 16. General operating conditions (continued) Symbol VDD (3)(4) VDDA VBAT Typ Max (2) - 3.6 1.7(2) - 2.4 2.4 - 3.6 - 1.65 - 3.6 USB not used 1.7 - 3.6 3 - 3.6 Power Scale 3 ((VOS[1:0] bits in PWR_CR register = 0x01), 120 MHz HCLK max frequency 1.08 1.14 1.20 Power Scale 2 ((VOS[1:0] bits in PWR_CR register = 0x10), 144 MHz HCLK max frequency with over-drive OFF or 168 MHz with over-drive ON 1.20 1.26 1.
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Electrical characteristics STM32F446xC/E 1. The over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 V. 2. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.16.2: Internal reset OFF). 3. When the ADC is used, refer to Table 74: ADC characteristics. 4. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V. 5. It is recommended to power VDD and VDDA from the same source.
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STM32F446xC/E Electrical characteristics Figure 20. External capacitor CEXT & (65 5 /HDN 06 9 1. Legend: ESR is the equivalent series resistance. Table 18. VCAP_1/VCAP_2 operating conditions(1) Symbol Parameter Conditions CEXT Capacitance of external capacitor 2.2 µF ESR ESR of external capacitor <2Ω CEXT Capacitance of external capacitor with a single VCAP pin available 4.7 µF ESR ESR of external capacitor with a single VCAP pin available <1Ω 1.
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Electrical characteristics 6.3.5 STM32F446xC/E Reset and power control block characteristics The parameters given in Table 21 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 16. Table 21. reset and power control block characteristics Symbol Parameter Conditions Programmable voltage detector level selection VPVD VPVDhyst(1) PVD hysteresis Max Unit PLS[2:0]=000 (rising edge) 2.09 2.14 2.19 V PLS[2:0]=000 (falling edge) 1.98 2.
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STM32F446xC/E Electrical characteristics Table 21. reset and power control block characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit IRUSH(1) InRush current on voltage regulator poweron (POR or wakeup from Standby) - 160 200 mA ERUSH(1) InRush energy on voltage regulator power- VDD = 1.7 V, TA = 105 °C, on (POR or wakeup IRUSH = 171 mA for 31 µs from Standby) - - 5.4 µC 1. Guaranteed based on test during characterization. 2.
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Electrical characteristics STM32F446xC/E Typical and maximum current consumption The MCU is placed under the following conditions: 82/202 Downloaded from Arrow.com. • All I/O pins are in input mode with a static value at VDD or VSS (no load). • All peripherals are disabled except if it is explicitly mentioned. • The Flash memory access time is adjusted both to fHCLK frequency and VDD range (see Table 17: Limitations depending on the operating power supply range).
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STM32F446xC/E Electrical characteristics Table 23.
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Electrical characteristics STM32F446xC/E Table 24. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled with prefetch) or RAM(1) Max(2) Symbol Parameter Conditions fHCLK (MHz) Typ 180 168(5) External clock, PLL ON, all peripherals enabled(3)(4) HSI, PLL OFF, all peripherals enabled(3)(4) IDD Supply current in RUN mode External clock, PLL ON, all Peripherals disabled(3) TA = 25 °C TA = 85 °C TA = 105 °C 86 93.0 115.
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STM32F446xC/E Electrical characteristics Table 25. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) Max(1) Symbol Parameter Conditions External clock, PLL ON, all peripherals enabled(2)(3) IDD Supply current in RUN mode External clock, PLL ON, all Peripherals disabled(2)(3) fHCLK (MHz) Typ 180 81 89.0 110.0 120.0 168(4) 74 80.2 105.7 112.0 150 69 74.9 99.5 105.6 144(4) 63 69.3 92.4 98.
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Electrical characteristics STM32F446xC/E Table 26. Typical and maximum current consumption in Sleep mode(1) Max Symbol Parameter Conditions fHCLK (MHz) Typ 180 TA = 25 °C TA = 25 °C TA = 25 °C 51.2 59.00 77.25 102.00 46.8 53.94 66.48 79.40 150 42.2 49.26 60.84 73.41 144(2) 38.6 45.37 55.47 66.96 120 29.3 35.70 42.49 51.46 90 22.8 29.17 34.78 43.12 60 16.3 22.41 27.12 34.83 30 10.1 16.03 19.72 26.86 25 9.0 14.92 18.41 25.38 16 6.5 13.10 15.1 22.
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STM32F446xC/E Electrical characteristics Table 26. Typical and maximum current consumption in Sleep mode(1) (continued) Max Symbol Parameter Conditions fHCLK (MHz) Typ 180 TA = 25 °C TA = 25 °C TA = 25 °C 11.36 17.59 28.2 51.6 168(2) 10.20 16.19 22.0 31.8 150 9.53 15.59 21.1 30.9 8.90 14.87 19.7 28.4 120 7.35 13.24 16.5 23.3 90 6.39 12.40 15.3 21.9 60 5.28 11.17 14.1 20.7 30 4.43 10.31 13.1 19.6 25 4.23 10.12 12.85 19.30 180 8.3 13.44 30.72 37.20 7.
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Electrical characteristics STM32F446xC/E Table 26. Typical and maximum current consumption in Sleep mode(1) (continued) Max Symbol Parameter Conditions Flash on IDD Supply current in Sleep mode Flash in HSI, PLL Deep off, all Power peripherals Down disabled mode Flash in STOP mode fHCLK (MHz) Typ 16 TA = 25 °C TA = 25 °C TA = 25 °C 3.89 4.93 11.72 18.54 8 2.45 3.29 11.66 18.46 4 1.69 2.56 11.60 18.40 2 1.28 2.22 11.57 18.37 16 1.0 6.65 16.54 19.50 8 0.9 6.93 16.
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STM32F446xC/E Electrical characteristics Table 27. Typical and maximum current consumptions in Stop mode Max Typ Symbol Parameter TA = 25 °C(1) TA = 85 °C TA = 105 °C(1) 0.234 1.2 10 16 0.205 1 9.5 15 0.15 0.95 8.5 14 0.121 0.9 6 12 Flash memory in Deep power down mode, main regulator in under-drive mode, all oscillators OFF, no independent watchdog 0.119 0.
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Electrical characteristics STM32F446xC/E Table 28. Typical and maximum current consumptions in Standby mode Typ(1) Symbol Parameter Max(2) TA = 25 °C TA = 25 °C Conditions VDD= 2.4 V VDD = 3.3 V Backup SRAM ON, and LSE oscillator in low power mode 2.43 3.44 4.12 7 20 36 Backup SRAM OFF, RTC ON and LSE oscillator in low power mode 1.81 2.81 3.33 6 17 31 3.32 4.33 4.95 8 21 37 Unit VDD = 3.3 V µA 2.57 3.59 4.16 7 18 32 Backup SRAM ON, RTC and LSE OFF 2.03 2.73 3.
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STM32F446xC/E Electrical characteristics Table 29. Typical and maximum current consumptions in VBAT mode Max(2) Typ Symbol Parameter Backup domain IDD_VBAT supply current TA = 85 °C TA = 25 °C Conditions(1) TA = 105 °C VBAT = 1.7 V VBAT= 2.4 V VBAT = 3.3 V VBAT = 3.6 V Backup SRAM ON, RTC ON and LSE oscillator in low power mode 1.46 1.62 1.83 6 11 Backup SRAM OFF, RTC ON and LSE oscillator in low power mode 0.72 0.85 1.
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Electrical characteristics STM32F446xC/E Figure 22. Typical VBAT current consumption (RTC ON/backup RAM OFF and LSE in high drive mode) Additional current consumption The MCU is placed under the following conditions: • All I/O pins are configured in analog mode. • The Flash memory access time is adjusted to fHCLK frequency. • The voltage scaling is adjusted to fHCLK frequency as follows: – 92/202 Downloaded from Arrow.com.
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STM32F446xC/E Electrical characteristics Table 30. Typical current consumption in Run mode, code with data processing running from Flash memory or RAM, regulator ON (ART accelerator enabled except prefetch), VDD=1.7 V(1) Max Symbol Parameter Conditions All Peripherals enabled IDD Supply current in Run mode from VDD supply All Peripherals disabled fHCLK (MHz) Typ 168 TA = 25 °C TA = 85 °C TA = 105 °C 65.11 70.0 79.7 90.0 150 58.31 62.8 73.4 79.9 144 53.14 57.1 69.9 75.3 120 39.
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Electrical characteristics STM32F446xC/E Table 31. Typical current consumption in Run mode, code with data processing running from Flash memory, regulator OFF (ART accelerator enabled except prefetch)(1) Symbol Parameter Conditions All Peripherals enabled IDD12 / IDD Supply current in Run mode from V12 and VDD supply All Peripherals disabled fHCLK (MHz) VDD=3.3 V VDD=1.7 V Unit IDD12 IDD IDD12 IDD 168 61.72 1.6 60.15 1.5 150 51.69 1.5 55.46 1.4 144 51.45 1.5 50.94 1.3 120 38.
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STM32F446xC/E Electrical characteristics Table 32. Typical current consumption in Sleep mode, regulator ON, VDD=1.7 V(1) Max Symbol Parameter Conditions All Peripherals enabled Flash on IDD Supply current in Sleep mode from VDD supply All Peripherals disabled, flash on fHCLK (MHz) Typ 168 TA = 25 °C TA = 85 °C TA = 105 °C 43.7 47.5 66.5 79.3 150 39.2 42.7 60.7 73.3 144 35.7 38.8 55.3 66.9 120 26.5 28.6 41.8 51.6 90 20.0 21.91 33.85 43.20 60 13.6 15.2 25.8 34.
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Electrical characteristics STM32F446xC/E Table 33. Typical current consumption in Sleep mode, regulator OFF(1) VDD=3.3 V Symbol Parameter Conditions All Peripherals enabled IDD12/IDD Supply current in Sleep mode from V12 and VDD supply All Peripherals disabled fHCLK (MHz) VDD=1.7 V IDD12 IDD IDD12 IDD 180 47.605 1.2 NA NA 168 44.35 1.0 41.53 0.8 150 40.58 0.9 39.96 0.8 144 35.68 0.9 34.60 0.7 120 27.30 0.9 29.11 0.7 90 20.69 0.8 19.78 0.6 60 13.88 0.7 13.
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STM32F446xC/E Caution: Electrical characteristics Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.
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Electrical characteristics STM32F446xC/E Table 34. Switching output I/O current consumption(1) (continued) I/O toggling Symbol Parameter Conditions VDD = 3.3 V CEXT = 10 pF C = CINT + CEXT + CS IDDIO I/O switching Current VDD = 3.3 V CEXT = 22 pF C = CINT + CEXT + CS VDD = 3.3 V CEXT = 33 pF C = CINT + Cext + CS frequency (fsw) Typ 2 MHz 0.18 8 MHz 0.67 25 MHz 2.09 50 MHz 3.6 60 MHz 4.5 84 MHz 7.8 90 MHz 9.8 2 MHz 0.26 8 MHz 1.01 25 MHz 3.14 50 MHz 6.39 60 MHz 10.
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STM32F446xC/E Electrical characteristics Table 35. Peripheral current consumption IDD(Typ Appli) Peripheral AHB1 AHB2 AHB3 Unit Scale 1 + OverDrive Scale 2 Scale 3 GPIOA 2.29 2.14 1.89 GPIOB 2.29 2.13 1.89 GPIOC 2.33 2.17 1.93 GPIOD 2.34 2.19 1.94 GPIOE 2.39 2.19 1.93 GPIOF 2.31 2.14 1.91 GPIOG 2.36 2.19 1.94 GPIOH 2.13 1.98 1.75 CRC 0.53 0.51 0.46 BKPSRAM 0.76 0.72 0.65 DMA1(1) 2.39N + 4.13 2.23N+3.56 1.97N+3.51 DMA2(1) 2.39N + 4.45 2.19N+3.72 2.
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Electrical characteristics STM32F446xC/E Table 35. Peripheral current consumption (continued) IDD(Typ Appli) Peripheral Scale 2 Scale 3 TIM2 18.18 16.92 15.07 TIM3 14.49 13.47 12.00 TIM4 15.18 14.11 12.50 TIM5 16.91 15.69 14.07 TIM6 2.69 2.47 2.20 TIM7 2.56 2.44 2.17 TIM12 7.07 6.56 5.83 TIM13 4.96 4.64 4.07 TIM14 5.09 4.72 4.27 WWDG 1.07 1.00 0.93 (2) 1.89 1.78 1.57 SPI3(2) 1.93 1.81 1.67 SPDIFRX 6.91 6.44 5.80 USART2 4.20 3.83 3.40 USART3 4.
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STM32F446xC/E Electrical characteristics Table 35. Peripheral current consumption (continued) IDD(Typ Appli) Peripheral APB2 Unit Scale 1 + OverDrive Scale 2 Scale 3 TIM1 17.51 16.28 14.43 TIM8 18.40 17.10 15.22 USART1 4.53 4.21 3.72 USART6 4.53 4.21 3.72 ADC1 4.69 4.35 3.85 ADC2 4.70 4.35 3.87 ADC3 4.66 4.31 3.82 SDIO 9.06 8.38 7.47 SPI1 1.97 1.89 1.67 SPI4 1.88 1.75 1.57 SYSCFG 1.51 1.40 1.23 TIM9 8.17 7.64 6.77 TIM10 5.07 4.75 4.22 TIM11 5.
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Electrical characteristics STM32F446xC/E Table 36. Low-power mode wakeup timings Symbol Parameter tWUSLEEP(2) TWUSLEEPFDSM (1) tWUSTOP(2) tWUSTOP(2) tWUSTDBY(2)(3) Conditions Typ(1) Max(1) Unit CPU clock cycle Wakeup from Sleep - 6 6 Wakeup from Sleep with Flash memory in Deep power down mode - 33.5 50 Main regulator is ON 12.8 15 Main regulator is ON and Flash memory in Deep power down mode 104.9 115 Low power regulator is ON 20.
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STM32F446xC/E Electrical characteristics Table 37. High-speed external user clock characteristics Symbol Parameter Conditions fHSE_ext External user clock source frequency(1) VHSEH OSC_IN input pin high level voltage VHSEL OSC_IN input pin low level voltage tw(HSE) tw(HSE) OSC_IN high or low time(1) Min Typ Max Unit 1 - 50 MHz 0.7VDD - VDD VSS - 0.
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Electrical characteristics STM32F446xC/E Figure 23. High-speed external clock source AC timing diagram 6(3%( 6(3%, TR (3% TF (3% T7 (3% /3#?). ), T7 (3% T 4(3% %XTERNAL CLOCK SOURCE F(3%?EXT 34- & AI Figure 24.
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STM32F446xC/E Electrical characteristics Table 39. HSE 4-26 MHz oscillator characteristics (1) Symbol Parameter fOSC_IN RF IDD Conditions Min Typ Max Unit Oscillator frequency - 4 - 26 MHz Feedback resistor - - 200 - kΩ VDD=3.3 V, ESR= 30 Ω, CL=5 pF@25 MHz - 450 - VDD=3.
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Electrical characteristics STM32F446xC/E possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 40. LSE oscillator characteristics (fLSE = 32.768 kHz) (1) Symbol RF IDD ACCLSE (2) Gm_crit_max tSU(LSE)(3) Parameter Conditions Min Typ Max Unit Feedback resistor - - 18.
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STM32F446xC/E 6.3.10 Electrical characteristics Internal clock source characteristics The parameters given in Table 41 and Table 42 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 16. High-speed internal (HSI) RC oscillator Table 41. HSI oscillator characteristics (1) Symbol fHSI Parameter Conditions Min Typ Max Unit - - 16 - MHz - - 1 % -8 - 4.
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Electrical characteristics STM32F446xC/E Low-speed internal (LSI) RC oscillator Table 42. LSI oscillator characteristics (1) Symbol Parameter fLSI(2) tsu(LSI) Frequency Min Typ Max Unit 17 32 47 kHz (3) LSI oscillator startup time - 15 40 µs (3) LSI oscillator power consumption - 0.4 0.6 µA IDD(LSI) 1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified. 2. Guaranteed based on test during characterization.. 3. Guaranteed by design. Figure 28.
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STM32F446xC/E Electrical characteristics Table 43. Main PLL characteristics (continued) Symbol Min Typ Max VCO freq = 100 MHz 75 - 200 VCO freq = 432 MHz 100 - 300 - 25 - - ±150 - - 15 - peak to peak - ±200 - Bit Time CAN jitter Cycle to cycle at 1 MHz on 1000 samples - 330 - IDD(PLL)(4) PLL power consumption on VDD VCO freq = 100 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLL)(4) PLL power consumption on VDDA VCO freq = 100 MHz VCO freq = 432 MHz 0.30 0.
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Electrical characteristics STM32F446xC/E Table 44. PLLI2S (audio PLL) characteristics (continued) Symbol Parameter Conditions IDD(PLLI2S)(4) PLLI2S power consumption on VDD VCO freq = 100 MHz VCO freq = 432 MHz IDDA(PLLI2S)(4) PLLI2S power consumption on VDDA VCO freq = 100 MHz VCO freq = 432 MHz Min Typ Max Unit 0.15 0.45 - 0.40 0.75 mA - 0.40 0.85 mA 0.30 0.55 1. Take care of using the appropriate division factor M to have the specified PLL input clock values. 2.
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STM32F446xC/E Electrical characteristics Table 46. SSCG parameters constraint Symbol Parameter Min Typ Max(1) Unit fMod Modulation frequency - - 10 KHz md Peak modulation depth 0.25 - 2 % - 15 MODEPER * INCSTEP - - 2 −1 - 1. Guaranteed by design. Equation 1 The frequency modulation period (MODEPER) is given by the equation below: MODEPER = round [ f PLL_IN ⁄ ( 4 × f Mod ) ] fPLL_IN and fMod must be expressed in Hz.
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Electrical characteristics STM32F446xC/E Figure 29 and Figure 30 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 29. PLL output clock waveforms in center spread mode &REQUENCY 0,,?/54 MD & MD TMODE 4IME XTMODE AI Figure 30. PLL output clock waveforms in down spread mode )UHTXHQF\ 3//B287 ) [PG WPRGH 7LPH [WPRGH DL E 6.3.
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STM32F446xC/E Electrical characteristics Table 48.
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Electrical characteristics STM32F446xC/E Table 49. Flash memory programming with VPP (continued) Symbol Parameter Conditions Min(1) Typ Max(1) Unit VPP VPP voltage range - 7 - 9 V IPP Minimum current sunk on the VPP pin - 10 - - mA Cumulative time during which VPP is applied - - - 1 hour tVPP(3) 1. Guaranteed by design. 2. The maximum programming time is measured after 100K erase operations. 3. VPP should only be connected during programming/erasing. Table 50.
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STM32F446xC/E Electrical characteristics Table 51. EMS characteristics Symbol Parameter Conditions VFESD VDD = 3.3 V, LQFP144, TA = Voltage limits to be applied on any I/O pin to +25 °C, fHCLK = 168 MHz, conforms induce a functional disturbance to IEC 61000-4-2 VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance Level/ Class 2B VDD = 3.
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Electrical characteristics STM32F446xC/E Table 52. EMI characteristics Symbol Parameter Max vs. [fHSE/fCPU] Monitored frequency band Conditions Unit 8/180 MHz VDD = 3.3 V, TA = 25 °C, LQFP144 package, conforming to SAE J1752/3 EEMBC, ART ON, all peripheral clocks enabled, clock dithering disabled. SEMI Peak level VDD = 3.3 V, TA = 25 °C, LQFP144 package, conforming to SAE J1752/3 EEMBC, ART ON, all peripheral clocks enabled, clock dithering enabled 6.3.15 0.
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STM32F446xC/E Electrical characteristics These tests are compliant with EIA/JESD 78A IC latchup standard. Table 54. Electrical sensitivities Symbol LU 6.3.16 Parameter Static latch-up class Conditions Class TA = +105 °C conforming to JESD78A II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation.
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Electrical characteristics 6.3.17 STM32F446xC/E I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 56: I/O static characteristics are derived from tests performed under the conditions summarized in Table 16. All I/Os are CMOS and TTL compliant. Table 56. I/O static characteristics Symbol VIL Parameter - BOOT0 I/O input low level voltage 1.75 V ≤ VDD ≤ 3.6 V, – 40 °C≤ TA ≤ 105 °C - - 1.7 V ≤ VDD ≤ 3.
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STM32F446xC/E Electrical characteristics Table 56.
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Electrical characteristics STM32F446xC/E Figure 31.
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STM32F446xC/E Electrical characteristics Table 57.
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Electrical characteristics STM32F446xC/E Table 58. I/O AC characteristics(1)(2) (continued) OSPEEDR y[1:0] bit value(1) Symbol fmax(IO)out Parameter Maximum frequency(3) 01 tf(IO)out/ tr(IO)out fmax(IO)out Output high to low level fall time and output low to high level rise time Maximum frequency(3) 10 tf(IO)out/ tr(IO)out fmax(IO)out Output high to low level fall time and output low to high level rise time Maximum frequency(3) 11 tf(IO)out/ tr(IO)out - 122/202 Downloaded from Arrow.
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STM32F446xC/E Electrical characteristics 1. Guaranteed by design. 2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register. 3. The maximum frequency is defined in Figure 32. 4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used. Figure 32.
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Electrical characteristics STM32F446xC/E Figure 33. Recommended NRST pin protection 9'' ([WHUQDO UHVHW FLUFXLW 538 1567 ,QWHUQDO 5HVHW )LOWHU ) 670 ) DL F 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 59. Otherwise the reset is not taken into account by the device. 3. The external capacitor on NRST must be placed as close as possible to the device. 6.3.
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STM32F446xC/E Electrical characteristics The I2C characteristics are described in Table 61. Refer also to Section 6.3.17: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 61. I2C characteristics Symbol Parameter Standard mode I2C(1)(2) Fast mode I2C(1)(2) Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.
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Electrical characteristics STM32F446xC/E Figure 34. I2C bus AC waveforms and measurement circuit s ''B, & s ''B, & 53 53 670 )[[ 56 6'$ ,ð& EXV 56 6&/ 67$57 5(3($7(' 67$57 67$57 WVX 67$ 6'$ WI 6'$ WU 6'$ WK 67$ WVX 6'$ WZ 6&/+ WZ 672 67$ 6723 WK 6'$ 6&/ WZ 6&// WU 6&/ WI 6&/ WVX 672 DL F 1. RS = series protection resistor. 2. RP = external pull-up resistor. 3. VDD_I2C is the I2C bus power supply. 126/202 Downloaded from Arrow.com.
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STM32F446xC/E Electrical characteristics FMPI2C characteristics The FMPI2C characteristics are described in Table 62. Refer also to Section 6.3.17: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 62. FMPI2C characteristics(1) Standard mode - fFMPI2CC Fast mode Fast+ mode Parameter Unit Min Max Min Max Min Max 2 - 8 - 17 16(2) - FMPI2CCLK frequency tw(SCLL) SCL clock low time 4.7 - 1.3 - 0.
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Electrical characteristics STM32F446xC/E Figure 35. FMPI2C timing diagram and measurement circuit s ''B, & s ''B, & 53 53 670 )[[ 56 6'$ ,ð& EXV 56 6&/ 67$57 5(3($7(' 67$57 67$57 WVX 67$ 6'$ WI 6'$ WU 6'$ WK 67$ WVX 6'$ WZ 6&/+ WZ 672 67$ 6723 WK 6'$ 6&/ WZ 6&// WU 6&/ WI 6&/ WVX 672 DL F 128/202 Downloaded from Arrow.com.
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STM32F446xC/E Electrical characteristics SPI interface characteristics Unless otherwise specified, the parameters given in Table 63 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 16, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C=30pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.
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Electrical characteristics STM32F446xC/E Table 63. SPI dynamic characteristics(1) (continued) Symbol tw(SCKH) Parameter Conditions Min Typ Max TPCLK TPCLK + 1.5 - - SCK high and low time Master mode, SPI presc = 2 TPCLK - 1.
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STM32F446xC/E Electrical characteristics Figure 37. SPI timing diagram - slave mode and CPHA = 1 166 LQSXW 6&. LQSXW W68 166 &3+$ &32/ &3+$ &32/ WK 166 WF 6&. WZ 6&.+ WZ 6&./ WK 62 WY 62 WD 62 0,62 287387 06% 287 WGLV 62 %,7 287 /6% 287 WK 6, WVX 6, 026, ,1387 WU 6&. WI 6&. 06% ,1 %,7 ,1 /6% ,1 DL E Figure 38. SPI timing diagram - master mode +LJK 166 LQSXW 6&. 2XWSXW &3+$ &32/ 6&. 2XWSXW WF 6&.
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Electrical characteristics STM32F446xC/E QSPI interface characteristics Unless otherwise specified, the parameters given in Table 64 for QSPI are derived from tests performed under the ambient temperature, fAHB frequency and VDD supply voltage conditions summarized in Table 16, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C=20pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.
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STM32F446xC/E Electrical characteristics Table 65. QSPI dynamic characteristics in DDR Mode(1) (continued) Symbol Parameter Conditions QSPI clock high and low - ts(IN) Data input setup time th(IN) Data input hold time tw(CKH) tw(CKL) tv(OUT) Data output valid time th(OUT) Data output hold time Min Typ Max (T(CK) / 2) - 2 - T(CK) / 2 T(CK) / 2 - (T(CK) / 2) +2 - 0 - - - 5.5 - - 2.7V
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Electrical characteristics STM32F446xC/E Table 66. I2S dynamic characteristics(1) (continued) Symbol Parameter Conditions Min Max tv(WS) WS valid time Master mode - 5.5 th(WS) WS hold time Master mode 1 - 1 - PCM short pulse Slave mode 2 - Slave mode 3 - 1.5 - Master receiver 3 - Slave receiver 2.5 - Master receiver 4 - Slave receiver 1 - Slave transmitter (after enable edge) - 16 Master transmitter (after enable edge) - 4.
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STM32F446xC/E Electrical characteristics Figure 39. I2S slave timing diagram (Philips protocol)(1) tc(CK) CK Input CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(2) MSB transmit Bitn transmit tsu(SD_SR) LSB receive(2) SDreceive th(SD_ST) LSB transmit th(SD_SR) MSB receive Bitn receive LSB receive ai14881b 1. .LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 40.
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Electrical characteristics STM32F446xC/E SAI characteristics Unless otherwise specified, the parameters given in Table 67 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 16, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C=30 pF • Measurement points are performed at CMOS levels: 0.5VDD Refer to Section 6.3.
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STM32F446xC/E Electrical characteristics Figure 41. SAI master timing waveforms F3#+ 3!)?3#+?8 TH &3 3!)?&3?8 OUTPUT TV &3 TH 3$?-4 TV 3$?-4 3!)?3$?8 TRANSMIT 3LOT N 3LOT N TSU 3$?-2 TH 3$?-2 3!)?3$?8 RECEIVE 3LOT N -3 6 Figure 42.
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Electrical characteristics STM32F446xC/E Table 69. USB OTG full speed DC electrical characteristics Symbol Parameter Conditions USB OTG full speed VDDUSB transceiver operating voltage Input levels - 3.0(2) - 3.6 0.2 - - VDI(3) Differential input sensitivity VCM(3) Differential common mode Includes VDI range range 0.8 - 2.5 VSE(3) Single ended receiver threshold - 1.3 - 2.0 VOL Static output level low RL of 1.5 kΩ to 3.6 V(4) - - 0.3 2.8 - 3.6 17 21 24 0.65 1.1 2.
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STM32F446xC/E Electrical characteristics Table 70. USB OTG full speed electrical characteristics(1) Driver characteristics Symbol Parameter Conditions Rise time(2) tr Fall time tf (2) Rise/ fall time matching trfm VCRS Output signal crossover voltage ZDRV Output driver impedance(3) Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 110 % 1.3 2.0 V 28 44 Ω Driving high or low 1. Guaranteed by design. 2. Measured from 10% to 90% of the data signal.
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Electrical characteristics STM32F446xC/E Table 72. USB HS clock timing parameters(1) (continued) Symbol tSTART_DEV tSTART_HOST Parameter Clock startup time after the de-assertion of SuspendM Min Typ Max Peripheral - - 5.6 Host - - - - - - PHY preparation time after the first transition of the input clock tPREP Unit ms µs 1. Guaranteed by design. Figure 44. ULPI timing diagram #LOCK #ONTROL )N 5,0)?$)2 5,0)?.
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STM32F446xC/E 6.3.21 Electrical characteristics 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 74 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 16. Table 74. ADC characteristics Symbol VDDA Parameter Min Typ Max 1.7(1) - 3.6 (1) 1.7 - VDDA - 0 - 0.6 15 18 MHz 0.
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Electrical characteristics STM32F446xC/E Table 74. ADC characteristics (continued) Symbol fS(2) Parameter Conditions Sampling rate (fADC = 30 MHz, and tS = 3 ADC cycles) Min Typ Max Unit 12-bit resolution Single ADC - - 2 Msps 12-bit resolution Interleave Dual ADC mode - - 3.
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STM32F446xC/E Electrical characteristics Table 76. ADC static accuracy at fADC = 30 MHz(1) a Symbol ET Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fADC = 30 MHz, RAIN < 10 kΩ, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V, VDDA −VREF < 1.2 V Typ Max(2) ±2 ±5 ±1.5 ±2.5 ±1.5 ±3 ±1 ±2 ±1.5 ±3 Unit LSB 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
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Electrical characteristics STM32F446xC/E being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.17 does not affect the ADC accuracy. Figure 45.
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STM32F446xC/E Electrical characteristics Figure 46. Typical connection diagram using the ADC 670 ) 9'' 5$,1 9$,1 6DPSOH DQG KROG $'& FRQYHUWHU 97 9 5$'& $,1[ &SDUDVLWLF 97 9 ,/ $ ELW FRQYHUWHU & $'& DL 1. Refer to Table 74 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy.
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Electrical characteristics STM32F446xC/E General PCB design guidelines Power supply decoupling should be performed as shown in Figure 47 or Figure 48, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 47. Power supply and reference decoupling (VREF+ not connected to VDDA) 670 ) 95() ) Q) 9''$ ) Q) 966$ 95() DL E 1.
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STM32F446xC/E Electrical characteristics Figure 48. Power supply and reference decoupling (VREF+ connected to VDDA) 670 ) 95() 9''$ ) Q) 95() 966$ DL F 1. VREF+ and VREF– inputs are both available on UFBGA144. VREF+ is also available on LQFP100, LQFP144, and WLCSP81. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. 6.3.22 Temperature sensor characteristics Table 80.
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Electrical characteristics 6.3.23 STM32F446xC/E VBAT monitoring characteristics Table 82. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 50 - KΩ Q Ratio on VBAT measurement - 4 - - -1 - +1 % 5 - - µs Er (1) Error on Q TS_vbat(2)(2) ADC sampling time when reading the VBAT 1 mV accuracy 1. Guaranteed by design. 2. Shortest sampling time can be determined in the application by multiple iterations. 6.3.
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STM32F446xC/E Electrical characteristics Table 85. DAC characteristics (continued) Symbol VSSA RLOAD(2) Parameter Conditions Min Typ Max Unit Comments - 0 - 0 V - 5 - - Ground Resistive load Connected to VSSA DAC output buffer ON Connected to VDDA kΩ 25 - - - Impedance output with buffer OFF - - - 15 kΩ When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.
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Electrical characteristics STM32F446xC/E Table 85. DAC characteristics (continued) Symbol Parameter INL(4) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) Offset(4) Gain error(4) tSETTLING(4 ) Conditions Min Typ Max Unit - - - ±1 LSB Given for the DAC in 10-bit configuration. - - - ±4 LSB Given for the DAC in 12-bit configuration.
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STM32F446xC/E Electrical characteristics Figure 49. 12-bit buffered/non-buffered DAC %XIIHUHG QRQ EXIIHUHG '$& %XIIHU 5/2$' ELW GLJLWDO WR DQDORJ FRQYHUWHU '$&[B287 &/2$' DL G 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. DocID027107 Rev 6 151/202 175 Downloaded from Arrow.com.
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Electrical characteristics 6.3.26 STM32F446xC/E FMC characteristics Unless otherwise specified, the parameters given in Table 86 to Table 93 for the FMC interface are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 15, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitance load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.
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STM32F446xC/E Electrical characteristics Figure 50. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms TW .% &-#?.% TV ./%?.% T W ./% T H .%?./% &-#?./% &-#?.7% TV !?.% &-#?!; = T H !?./% !DDRESS TV ",?.% T H ",?./% &-#?.",; = T H $ATA?.% T SU $ATA?./% TH $ATA?./% T SU $ATA?.% $ATA &-#?$; = T V .!$6?.% TW .!$6 &-#?.!$6 &-#?.7!)4 TH .%?.7!)4 TSU .7!)4?.% -3 6 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
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Electrical characteristics STM32F446xC/E Table 86. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) Symbol Min Max 2THCLK – 2 2 THCLK + 0.5 0 1 2THCLK - 1 2THCLK + 0.5 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 0.
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STM32F446xC/E Electrical characteristics Figure 51. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms TW .% &-#?.%X &-#?./% TV .7%?.% TW .7% T H .%?.7% &-#?.7% TV !?.% &-#?!; = TH !?.7% !DDRESS TV ",?.% &-#?.",; = TH ",?.7% .", TV $ATA?.% TH $ATA?.7% $ATA &-#?$; = T V .!$6?.% &-#?.!$6 TW .!$6 &-#?.7!)4 TH .%?.7!)4 TSU .7!)4?.% -3 6 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. Table 88.
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Electrical characteristics STM32F446xC/E Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR write NWAIT timings(1)(2) Symbol Parameter Min Max FMC_NE low time 8THCLK - 0.5 8THCLK + 1 FMC_NWE low time 6THCLK - 0.5 6THCLK + 1 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK - 0.5 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK + 2 - tw(NE) tw(NWE) Unit ns 1. CL = 30 pF. 2. Guaranteed based on test during characterization. Figure 52.
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STM32F446xC/E Electrical characteristics Table 90. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Symbol tw(NE) tv(NOE_NE) ttw(NOE) th(NE_NOE) tv(A_NE) tv(NADV_NE) tw(NADV) Parameter Min Max 3THCLK – 2 3THCLK+0.5 2THCLK – 0.5 2THCLK THCLK – 1 THCLK + 0.5 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 2 FMC_NEx low to FMC_NADV low 0 2 THCLK – 0.5 THCLK + 0.
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Electrical characteristics STM32F446xC/E Figure 53. Asynchronous multiplexed PSRAM/NOR write waveforms TW .% &-#? .%X &-#?./% TV .7%?.% TW .7% T H .%?.7% &-#?.7% TH !?.7% TV !?.% &-#? !; = !DDRESS TV ",?.% &-#? .",; = .", T V !?.% &-#? !$; = TH ",?.7% T V $ATA?.!$6 !DDRESS TH $ATA?.7% $ATA TH !$?.!$6 T V .!$6?.% TW .!$6 &-#?.!$6 &-#?.7!)4 TH .%?.7!)4 TSU .7!)4?.% -3 6 158/202 Downloaded from Arrow.com.
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STM32F446xC/E Electrical characteristics Table 92. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) Parameter Min Max 4THCLK - 2 4THCLK+0.5 FMC_NEx low to FMC_NWE low THCLK THCLK + 0.5 FMC_NWE low time 2THCLK 2THCLK + 0.5 FMC_NWE high to FMC_NE high hold time THCLK - - 0 0.5 1 THCLK – 0.5 THCLK+ 0.
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Electrical characteristics STM32F446xC/E In all timing tables, the THCLK is the HCLK clock period (with maximum FMC_CLK = 90 MHz). Figure 54. Synchronous multiplexed NOR/PSRAM read timings "53452. TW #,+ TW #,+ &-#?#,+ $ATA LATENCY TD #,+, .%X, &-#?.%X T D #,+, .!$6, TD #,+( .%X( TD #,+, .!$6( &-#?.!$6 TD #,+, !6 TD #,+( !)6 &-#?!; = TD #,+, ./%, TD #,+( ./%( &-#?./% T D #,+, !$6 &-#?!$; = TD #,+, !$)6 TSU !$6 #,+( !$; = TH #,+( !$6 TSU !$6 #,+( $ TSU .7!)46 #,+( &-#?.
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STM32F446xC/E Electrical characteristics Table 94. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol tw(CLK) Parameter FMC_CLK period Min Max 2THCLK - - 2.5 THCLK - 0.5 - td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 2.
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Electrical characteristics STM32F446xC/E Figure 55. Synchronous multiplexed PSRAM write timings "53452. TW #,+ TW #,+ &-#?#,+ $ATA LATENCY TD #,+, .%X, TD #,+( .%X( &-#?.%X TD #,+, .!$6, TD #,+, .!$6( &-#?.!$6 TD #,+( !)6 TD #,+, !6 &-#?!; = TD #,+( .7%( TD #,+, .7%, &-#?.7% TD #,+, !$)6 TD #,+, !$6 &-#?!$; = TD #,+, $ATA TD #,+, $ATA !$; = $ $ &-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( TH #,+( .7!)46 TD #,+( .",( &-#?.
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STM32F446xC/E Electrical characteristics Table 95. Synchronous multiplexed PSRAM write timings(1)(2) Symbol Min Max 2THCLK - 1 - - 2.5 THCLK + 0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - - 2 THCLK - - 0 THCLK - 0.5 - tw(CLK) Parameter FMC_CLK period, VDD range= 2.7 to 3.6 V td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..
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Electrical characteristics STM32F446xC/E Figure 56. Synchronous non-multiplexed NOR/PSRAM read timings TW #,+ TW #,+ &-#?#,+ TD #,+, .%X, TD #,+( .%X( $ATA LATENCY &-#?.%X TD #,+, .!$6, TD #,+, .!$6( &-#?.!$6 TD #,+( !)6 TD #,+, !6 &-#?!; = TD #,+, ./%, TD #,+( ./%( &-#?./% TSU $6 #,+( TH #,+( $6 TSU $6 #,+( &-#?$; = TH #,+( $6 $ TSU .7!)46 #,+( &-#?.7!)4 7!)4#&' B 7!)40/, B $ TH #,+( .7!)46 TSU .7!)46 #,+( &-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( T H #,+( .
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STM32F446xC/E Electrical characteristics 1. CL = 30 pF. 2. Guaranteed based on test during characterization. Figure 57. Synchronous non-multiplexed PSRAM write timings TW #,+ TW #,+ &-#?#,+ TD #,+, .%X, TD #,+( .%X( $ATA LATENCY &-#?.%X TD #,+, .!$6, TD #,+, .!$6( &-#?.!$6 TD #,+( !)6 TD #,+, !6 &-#?!; = TD #,+, .7%, TD #,+( .7%( &-#?.7% TD #,+, $ATA TD #,+, $ATA $ &-#?$; = $ &-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( TD #,+( .",( TH #,+( .7!)46 &-#?.
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Electrical characteristics STM32F446xC/E Table 97. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol Min Max 2THCLK – 1 - - 2.5 THCLK – 0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - tw(CLK) Parameter FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..
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STM32F446xC/E Electrical characteristics Figure 58. NAND controller waveforms for read access &-#?.#%X !,% &-#?! #,% &-#?! &-#?.7% TD !,% ./% TH ./% !,% &-#?./% .2% TSU $ ./% TH ./% $ &-#?$; = -3 6 Figure 59. NAND controller waveforms for write access &-#?.#%X !,% &-#?! #,% &-#?! TH .7% !,% TD !,% .7% &-#?.7% &-#?./% .2% TV .7% $ TH .7% $ &-#?$; = -3 6 DocID027107 Rev 6 167/202 175 Downloaded from Arrow.com.
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Electrical characteristics STM32F446xC/E Figure 60. NAND controller waveforms for common memory read access &-#?.#%X !,% &-#?! #,% &-#?! TH ./% !,% TD !,% ./% &-#?.7% TW ./% &-#?./% TSU $ ./% TH ./% $ &-#?$; = -3 6 Figure 61. NAND controller waveforms for common memory write access &-#?.#%X !,% &-#?! #,% &-#?! TD !,% ./% TW .7% TH ./% !,% &-#?.7% &-#?. /% TD $ .7% TV .7% $ TH .7% $ &-#?$; = -3 6 Table 98.
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STM32F446xC/E Electrical characteristics Table 99. Switching characteristics for NAND Flash write cycles(1) Symbol tw(NWE) Parameter FMC_NWE low width Min Max Unit 4THCLK - 2 4THCLK ns 0 - ns tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 3THCLK – 1 - ns td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 5THCLK – 3 - ns - 3THCLK - 0.
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Electrical characteristics STM32F446xC/E Table 100. SDRAM read timings(1)(2) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2THCLK-0.5 2THCLK+0.5 tsu(SDCLKH _Data) Data input setup time 1 - th(SDCLKH_Data) Data input hold time 4 - td(SDCLKL_Add) Address valid time - 3 td(SDCLKL_ SDNE) Chip select valid time - 1.5 th(SDCLKL_SDNE) Chip select hold time 0 - td(SDCLKL_SDNRAS) SDNRAS valid time - 1.
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STM32F446xC/E Electrical characteristics Figure 63. SDRAM write access waveforms &-#?3$#,+ TD 3$#,+,?!DD# TH 3$#,+,?!DD2 TD 3$#,+,?!DD2 2OW N &-#?!> @ #OL #OL #OLI #OLN TH 3$#,+,?!DD# TH 3$#,+,?3.$% TD 3$#,+,?3.$% &-#?3$.%; = TH 3$#,+,?.2!3 TD 3$#,+,?.2!3 &-#?3$.2!3 TD 3$#,+,?.#!3 TH 3$#,+,?.#!3 TD 3$#,+,?.7% TH 3$#,+,?.7% &-#?3$.#!3 &-#?3$.7% TD 3$#,+,?$ATA $ATA &-#?$; = $ATA $ATAI $ATAN TH 3$#,+,?$ATA TD 3$#,+,?.", &-#?.",; = -3 6 Table 102.
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Electrical characteristics STM32F446xC/E Table 103. LPSDR SDRAM write timings(1)(2) Symbol Parameter Min Max Unit MHz F(SDCLK) Frequency of operation - 84 tw(SDCLK) FMC_SDCLK period 2THCLK - 0.5 2THCLK + 0.5 td(SDCLKL _Data) Data output valid time - 5 th(SDCLKL _Data) Data output hold time 0.5 - td(SDCLK _Add) Address valid time - 3 td(SDCLKL _SDNWE)) SDNWE valid time - 3 th(SDCLKL_SDNWE)) SDNWE hold time 0 - td(SDCLKL_SDNE)) Chip select valid time - 2.
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STM32F446xC/E Electrical characteristics Figure 64. DCMI timing diagram '&0,B3,;&/. '&0,B3,;&/. WK +6<1& WVX +6<1& '&0,B+6<1& WK +6<1& WVX 96<1& '&0,B96<1& WVX '$7$ WK '$7$ '$7$> @ 06 9 6.3.
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Electrical characteristics STM32F446xC/E Figure 66. SD default mode #+ T/6$ T/($ $ #-$ OUTPUT AI Table 105. Dynamic characteristics: SD / MMC characteristics(1)(2) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode - 0 - 50 MHz - SDIO_CK/fPCLK2 frequency ratio - - - 8/3 - tW(CKL) Clock low time fpp =50MHz 9.5 10.5 - tW(CKH) Clock high time fpp =50MHz 8.5 9.
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STM32F446xC/E Electrical characteristics Table 106. Dynamic characteristics: eMMC characteristics VDD = 1.7 V to 1.9 V(1)(2) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode - 0 - 50 MHz SDIO_CK/fPCLK2 frequency ratio - - - 8/3 - tW(CKL) Clock low time fpp =50MHz 9.5 10.5 - tW(CKH) Clock high time fpp =50MHz 8.5 9.5 - ns CMD, D inputs (referenced to CK) in eMMC mode tISU Input setup time HS fpp =50MHz 0.
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Package information 7 STM32F446xC/E Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 LQFP64 package information Figure 67.
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STM32F446xC/E Package information Table 108. LQFP64 – 10 x 10 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max D 11.800 12.000 12.200 0.4646 0.4724 0.4803 D1 9.800 10.000 10.200 0.3858 0.3937 0.4016 D3 - 7.500 - - 0.2953 - E 11.800 12.000 12.200 0.4646 0.4724 0.4803 E1 9.800 10.000 10.200 0.3858 0.3937 0.4016 E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.
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Package information STM32F446xC/E Device marking for LQFP64 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 69. LQFP64 marking example (package top view) 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ $ 670 ) 5(7 < :: 3LQ LGHQWLILHU 'DWH FRGH 06Y 9 1.
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STM32F446xC/E 7.2 Package information LQFP100 package information Figure 70. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline MM C ! ! ! 3%!4).' 0,!.% # '!5'% 0,!.% $ , $ ! + CCC # , $ 0). )$%.4)&)#!4)/. % % % B E ,?-%?6 1. Drawing is not to scale. Table 109. LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.
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Package information STM32F446xC/E Table 109. LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1.
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STM32F446xC/E Package information Device marking for LQFP100 package The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 72. LQFP100 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ 670 ) 5HYLVLRQ FRGH 9&7 $ 'DWH FRGH < :: 3LQ LGHQWLILHU 06Y 9 1.
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Package information 7.3 STM32F446xC/E LQFP144 package information. Figure 73. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline PP *$8*( 3/$1( C ! F $ ! $ ! $ 3%!4).' 0,!.% # FFF & MM CCC # ' $ ' $ ' $ / + , / , . ! $ '!5'% 0,!.% ( ( % ( % % E B 0). )$%.4)&)#!4)/. E 3,1 !?-%?6 ,'(17,),&$7,21 H $B0(B9 1. Drawing is not to scale. 182/202 Downloaded from Arrow.
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STM32F446xC/E Package information Table 110. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.874 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.
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Package information STM32F446xC/E Figure 74. LQFP144 recommended footprint DL H 1. Dimensions are expressed in millimeters. 184/202 Downloaded from Arrow.com.
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STM32F446xC/E Package information Device marking for LQFP144 package The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 75. LQFP144 marking example (package top view) 2SWLRQDO JDWH PDUN 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ $ 670 ) =(7 'DWH FRGH < :: 3LQ LGHQWLILHU 06Y 9 1.
PAGE 186
Package information 7.4 STM32F446xC/E UFBGA144 7 x 7 mm package information Figure 76. UFBGA144 - 144-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline = 6HDWLQJ SODQH GGG = $ $ $ $ $ ( H $ EDOO $ EDOO LGHQWLILHU LQGH[ DUHD ) ; ( $ ) ' ' H < 0 %27720 9,(: E EDOOV HHH 0 = < ; III 0 = 723 9,(: $ $6B0(B9 1. Drawing is not in scale. Table 111. UFBGA144 - 144-pin, 7 x 7 mm, 0.
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STM32F446xC/E Package information Table 111. UFBGA144 - 144-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 77. UFBGA144 - 144-ball, 7 x 7 mm, 0.
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Package information STM32F446xC/E Device marking for UFBGA144 7 x 7 mm package The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 78. UQFP144 7 x 7 mm marking example (package top view) 3URGXFW LGHQWLILFDWLRQ 670 ) =(+ 'DWH FRGH < :: %DOO $ LQGHQWLILHU $ $GGLWLRQDO LQIRUPDWLRQ 06Y 9 1.
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STM32F446xC/E 7.5 Package information UFBGA144 10 x 10 mm package information Figure 79. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package outline & 6HDWLQJ SODQH GGG = $ $ $ $ $ ( H $ EDOO $ EDOO LGHQWLILHU LQGH[ DUHD ) $ ( $ ) ' ' H % 0 %27720 9,(: E EDOOV HHH 0 & $ % III 0 & 723 9,(: $
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Package information STM32F446xC/E Table 113. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. F 0.550 0.600 0.650 0.0177 0.0197 0.0217 ddd - - 0.080 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 80. UFBGA144 - 144-pin, 10 x 10 mm, 0.
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STM32F446xC/E Package information Device marking for UFBGA144 10 x 10 mm package The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 81. UQFP144 10 x 10 mm marking example (package top view) 3URGXFW LGHQWLILFDWLRQ 670 ) =(- $ $GGLWLRQDO LQIRUPDWLRQ 'DWH FRGH < :: %DOO $ LQGHQWLILHU 06Y 9 1.
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Package information 7.6 STM32F446xC/E WLCSP81 package information Figure 82. WLCSP81 - 81-pin, 3.693 x 3.815 mm, 0.4 mm pitch wafer level chip scale package outline H EEE = $ EDOO ORFDWLRQ H $ EDOO ORFDWLRQ ' $ H 'HWDLO $ ( H - * %RWWRP YLHZ %XPS VLGH DDD $ ) 7RS YLHZ :DIHU EDFN VLGH $ $ 6LGH YLHZ 'HWDLO $ URWDWHG E\ $ HHH = T FFF 0 TGGG 0 E =;< = 6HDWLQJ SODQH = $ 7B0(B9 1. Drawing is not to scale. Table 115. WLCSP81- 81-pin, 3.693 x 3.815 mm, 0.
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STM32F446xC/E Package information Table 115. WLCSP81- 81-pin, 3.693 x 3.815 mm, 0.4 mm pitch wafer level chip scale package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max F - 0.2465 - - 0.0097 - G - 0.3075 - - 0.0121 - aaa - - 0.100 - - 0.0039 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package information STM32F446xC/E Device marking for WLCSP81 package The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 84. WLCSP81 10 x 10 mm marking example (package top view) 3LQ LGHQWLILHU 670 ) 3URGXFW LGHQWLILFDWLRQ 0&< 'DWH FRGH < :: $ $GGLWLRQDO LQIRUPDWLRQ 06Y 9 1.
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STM32F446xC/E 7.7 Package information Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: • TA max is the maximum ambient temperature in ° C, • ΘJA is the package junction-to-ambient thermal resistance, in ° C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts.
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Part numbering 8 STM32F446xC/E Part numbering Table 118.
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STM32F446xC/E Appendix A A.1 Application block diagrams Application block diagrams USB OTG full speed (FS) interface solutions Figure 85. USB controller configured as peripheral-only and used in Full speed mode 9''86% 9'' 9%86 '0 3$ 3% 26&B,1 '3 3$ 3% 966 26&B287 86% 6WG % FRQQHFWRU 9 WR 9''86% 9ROWDJH UHJXODWRU 06Y 9 1. External voltage regulator only needed when building a VBUS powered device. 2.
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Application block diagrams STM32F446xC/E Figure 87. USB controller configured in dual mode and used in full speed mode 6$$ 6 TO 6$$ VOLTAGE REGULATOR 6$$ '0)/ )21 /VERCURRENT #URRENT LIMITER POWER SWITCH 6 0WR 34- & XX 0! 0" 0! 0" /3#?). /3#?/54 0! 0" 0! 0" 6"53 $$0 )$ 633 53"MICRO !" CONNECTOR '0)/ %. -3 6 1. External voltage regulator only needed when building a VBUS powered device. 2.
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STM32F446xC/E A.2 Application block diagrams USB OTG high speed (HS) interface solutions Figure 88. USB controller configured as peripheral, host, or dual-mode and used in high speed mode 34- & XX &3 0(9 53" (3 /4' #TRL $0 $- NOT CONNECTED $0 5,0)?#,+ $- 5,0)?$; = 5,0) )$ 5,0)?$)2 6"53 5,0)?340 53" CONNECTOR 633 5,0)?.84 (IGH SPEED /4' 0(9 0,, 84 OR -(Z 84 -#/ OR -#/ 8) -3 6 1. It is possible to use MCO1 or MCO2 to save a crystal.
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Revision history STM32F446xC/E Revision history Table 119. Document revision history Date Revision 17-Feb-2015 1 Initial release. 2 Added note 2 inside Table 2 Updated Table 11, Table 23, Table 24, Table 25, Table 26, Table 30, Table 51, Table 52, Table 53, and Table 61 Added condition inside Typical and maximum current consumption and Additional current consumption Added FMPI2C characteristics Added Table 62 and Figure 35 3 Updated: – Section 6.3.
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STM32F446xC/E Revision history Table 119.
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STM32F446xC/E IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.