Datasheet
Application block diagrams STM32F427xx STM32F429xx
232/239 DocID024030 Rev 10
Figure 109. RMII with a 25 MHz crystal and PHY with PLL
1. f
HCLK
must be greater than 25 MHz.
2. The 25 MHz (PHY_CLK) must be derived directly from the HSE oscillator, before the PLL block.
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