Datasheet

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STM32F427xx STM32F429xx Electrical characteristics
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6.3.28 LCD-TFT controller (LTDC) characteristics
Unless otherwise specified, the parameters given in Table 107 for LCD-TFT are derived
from tests
performed under the ambient temperature, fHCLK frequency and VDD supply
voltage summarized in Table 1 7
, with the following configuration:
• LCD_CLK polarity: high
• LCD_DE polarity : low
• LCD_VSYNC and LCD_HSYNC polarity: high
•
Pixel formats: 24 bits
Table 107. LTDC characteristics
Symbol ParameterMinMaxUnit
f
CLK
LTDC clock output frequency - 83 MHz
D
CLK
LTDC clock output duty cycle 45 55 %
t
w(CLKH)
t
w(CLKL)
Clock High time, low time tw(CLK)/2 − 0.5 tw(CLK)/2+0.5
ns
t
v(DATA)
Data output valid time - 3.5
t
h(DATA)
Data output hold time 1.5 -
t
v(HSYNC)
HSYNC/VSYNC/DE output valid
time
-2.5t
v(VSYNC)
t
v(DE)
t
h(HSYNC)
HSYNC/VSYNC/DE output hold
time
2-t
h(VSYNC)
th(DE)
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