Datasheet

Electrical characteristics STM32F427xx STM32F429xx
168/239 DocID024030 Rev 10
Figure 54. 12-bit buffered /non-buffered DAC
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
t
WAKEUP
(
4)
Wakeup time from off
state (Setting the ENx
bit in the DAC Control
register)
--6.510µs
C
LOAD
≤ 50 pF, R
LOAD
≥ 5 kΩ
input code between lowest and
highest possible ones.
PSRR+
(2)
Power supply rejection
ratio (to V
DDA
) (static
DC measurement)
- - –67 –40 dB No R
LOAD
, C
LOAD
= 50 pF
1. V
DDA
minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2:
Internal reset OFF).
2. Guaranteed by design.
3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic
consumption occurs.
4. Guaranteed by characterization.
Table 85. DAC characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit Comments
DLD

%XIIHU
ELW
GLJLWDOWR
DQDORJ
FRQYHUWHU
%XIIHUHGQRQEXIIHUHG'$&
'$&[B287
5
/2$'
&/2$'
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