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This is information on a product in full production.

January 2018 DocID024030 Rev 10 1/239

STM32F427xx STM32F429xx

32b Arm

Cortex

-M4 MCU+FPU, 225DMIPS, up to 2MB Flash/256+4KB RAM, USB

OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 com. interfaces, camera & LCD-TFT

Datasheet - production data

Features

• Core: Arm

32-bit Cortex

-M4 CPU with FPU,

Adaptive real-time accelerator (ART

Accelerator™) allowing 0-wait state execution

from Flash memory, frequency up to 180 MHz,

MPU, 225 DMIPS/1.25 DMIPS/MHz

(Dhrystone 2.1), and DSP instructions

• Memories

– Up to 2 MB of Flash memory organized into

two banks allowing read-while-write

– Up to 256+4 KB of SRAM including 64-KB

of CCM (core coupled memory) data RAM

– Flexible external memory controller with up

to 32-bit data bus: SRAM, PSRAM,

SDRAM/LPSDR SDRAM, Compact

Flash/NOR/NAND memories

• LCD parallel interface, 8080/6800 modes

• LCD-TFT controller with fully programmable

resolution (total width up to 4096 pixels, total

height up to 2048 lines and pixel clock up to

83 MHz)

• Chrom-ART Accelerator™ for enhanced

graphic content creation (DMA2D)

• Clock, reset and supply management

– 1.7 V to 3.6 V application supply and I/Os

– POR, PDR, PVD and BOR

– 4-to-26 MHz crystal oscillator

– Internal 16 MHz factory-trimmed RC (1%

accuracy)

– 32 kHz oscillator for RTC with calibration

– Internal 32 kHz RC with calibration

• Low power

– Sleep, Stop and Standby modes

–V

BAT

supply for RTC, 20×32 bit backup

registers + optional 4 KB backup SRAM

• 3×12-bit, 2.4 MSPS ADC: up to 24 channels

and 7.2 MSPS in triple interleaved mode

• 2×12-bit D/A converters

• General-purpose DMA: 16-stream DMA

controller with FIFOs and burst support

• Up to 17 timers: up to twelve 16-bit and two 32-

bit timers up to 180 MHz, each with up to 4

IC/OC/PWM or pulse counter and quadrature

(incremental) encoder input

• Debug mode

– SWD & JTAG interfaces

– Cortex-M4 Trace Macrocell™

• Up to 168 I/O ports with interrupt capability

– Up to 164 fast I/Os up to 90 MHz

– Up to 166 5 V-tolerant I/Os

• Up to 21 communication interfaces

– Up to 3 × I

C interfaces (SMBus/PMBus)

– Up to 4 USARTs/4 UARTs (11.25 Mbit/s,

ISO7816 interface, LIN, IrDA, modem

control)

– Up to 6 SPIs (45 Mbits/s), 2 with muxed

full-duplex I

S for audio class accuracy via

internal audio PLL or external clock

– 1 x SAI (serial audio interface)

– 2 × CAN (2.0B Active) and SDIO interface

• Advanced connectivity

– USB 2.0 full-speed device/host/OTG

controller with on-chip PHY

– USB 2.0 high-speed/full-speed

device/host/OTG controller with dedicated

DMA, on-chip full-speed PHY and ULPI

– 10/100 Ethernet MAC with dedicated DMA:

supports IEEE 1588v2 hardware, MII/RMII

• 8- to 14-bit parallel camera interface up to

54 Mbytes/s

• True random number generator

• CRC calculation unit

• RTC: subsecond accuracy, hardware calendar

• 96-bit unique ID

LQFP100 (14 × 14 mm)

LQFP144 (20 × 20 mm)

UFBGA176 (10 x 10 mm)

LQFP176 (24 × 24 mm)

LQFP208 (28 x 28 mm)

WLCSP143

TFBGA216 (13 x 13 mm)

UFBGA169 (7 × 7 mm)

&"'!

www.st.com

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Summary of content (240 pages)

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STM32F427xx STM32F429xx 32b Arm® Cortex®-M4 MCU+FPU, 225DMIPS, up to 2MB Flash/256+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 com. interfaces, camera & LCD-TFT Datasheet - production data Features • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.
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STM32F427xx STM32F429xx Table 1. Device summary Reference Part number STM32F427xx STM32F427VG, STM32F427ZG, STM32F427IG, STM32F427AG, STM32F427VI, STM32F427ZI, STM32F427II, STM32F427AI STM32F429VG, STM32F429ZG, STM32F429IG, STM32F429BG, STM32F429NG, STM32F429AG, STM32F429VI, STM32F429ZI, STM32F429II,, STM32F429BI, STM32F429xx STM32F429NI,STM32F429AI, STM32F429VE, STM32F429ZE, STM32F429IE, STM32F429BE, STM32F429NE 2/239 Downloaded from Arrow.com.
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STM32F427xx STM32F429xx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 3 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.
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Contents STM32F427xx STM32F429xx 3.22 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.22.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.22.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.22.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.22.4 Independent watchdog . . . . . . . . . . . . . . . .
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STM32F427xx STM32F429xx Contents 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.
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Contents STM32F427xx STM32F429xx 6.3.30 7 8 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 7.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 7.2 WLCSP143 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 7.3 LQFP144 package information . . . . . . . . . . . . .
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STM32F427xx STM32F429xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Device summary . . . . . . . . . .
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List of tables Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92.
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STM32F427xx STM32F429xx Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. List of tables Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . .
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List of figures STM32F427xx STM32F429xx List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42.
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STM32F427xx STM32F429xx Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87.
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List of figures Figure 90. Figure 91. Figure 92. Figure 93. Figure 94. Figure 95. Figure 96. Figure 97. Figure 98. Figure 99. Figure 100. Figure 101. Figure 102. Figure 103. Figure 104. Figure 105. Figure 106. Figure 107. Figure 108. Figure 109. 12/239 Downloaded from Arrow.com. STM32F427xx STM32F429xx LQFP176 - 176-pin, 24 x 24 mm low profile quad flat recommended footprint. . . . . . . . . 211 LQFP176 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F427xx STM32F429xx 1 Introduction Introduction This datasheet provides the description of the STM32F427xx and STM32F429xx line of microcontrollers. For more details on the whole STMicroelectronics STM32 family, please refer to Section 2.1: Full compatibility throughout the family. The STM32F427xx and STM32F429xx datasheet should be read in conjunction with the STM32F4xx reference manual.
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Description 2 STM32F427xx STM32F429xx Description The STM32F427xx and STM32F429xx devices are based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 180 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all Arm® singleprecision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.
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STM32F427xx STM32F429xx Description These features make the STM32F427xx and STM32F429xx microcontrollers suitable for a wide range of applications: • Motor drive and application control • Medical equipment • Industrial applications: PLC, inverters, circuit breakers • Printers, and scanners • Alarm systems, video intercom, and HVAC • Home audio appliances Figure 4 shows the general block diagram of the device family. DocID024030 Rev 10 15/239 44 Downloaded from Arrow.com.
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/239 Downloaded from Arrow.com.
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Downloaded from Arrow.com. STM32F429Vx 1.8 to 3.6 V(3) 180 MHz Yes 2 STM32F427 STM32F429 STM32F427 Ax Ax Ix LQFP208 STM32F429Bx TFBGA216 STM32F429Nx 3. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section 3.17.2: Internal reset OFF). The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
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Description 2.1 STM32F427xx STM32F429xx Full compatibility throughout the family The STM32F427xx and STM32F429xx devices are part of the STM32F4 family. They are fully pin-to-pin, software and feature compatible with the STM32F2xx devices, allowing the user to try different memory densities, peripherals, and performances (FPU, higher frequency) for a greater degree of freedom during the development cycle.
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STM32F427xx STM32F429xx Description Figure 2. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package 966 UHVLVWRU RU VROGHULQJ EULGJH SUHVHQW IRU WKH 670 ) [[ FRQILJXUDWLRQ QRW SUHVHQW LQ WKH 670 ) [[ FRQILJXUDWLRQ 966 966 6LJQDO IURP H[WHUQDO SRZHU VXSSO\ VXSHUYLVRU 1RW SRSXODWHG ZKHQ UHVLVWRU RU VROGHULQJ EULGJH SUHVHQW 3'5B21 966 9'' 966 1RW SRSXODWHG IRU 670 ) [[ 7ZR UHVLVWRUV FRQQHFWH
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Description STM32F427xx STM32F429xx Figure 4.
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STM32F427xx STM32F429xx Functional overview 3 Functional overview 3.1 Arm® Cortex®-M4 with FPU and embedded Flash and SRAM The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
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Functional overview 3.4 STM32F427xx STM32F429xx Embedded Flash memory The devices embed a Flash memory of up to 2 Mbytes available for storing programs and data. 3.5 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity.
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STM32F427xx STM32F429xx Functional overview Figure 5. STM32F427xx and STM32F429xx Multi-AHB matrix &KURP $57 $FFHOHUDWRU '0$ ' ,&2'( '&2'( $&&(/ '0$ ' /&' 7)7B0 86%B+6B0 0$& 86% 27* /&' 7)7 (WKHUQHW +6 (7+(51(7B0 '0$B3 *3 '0$ '0$B0(0 '0$B0(0 *3 '0$ '0$B3, 6 EXV ' EXV $50 &RUWH[ 0 , EXV .E\WH &&0 GDWD 5$0 )ODVK PHPRU\ 65$0 .E\WH 65$0 .E\WH 65$0 .E\WH $+% SHULSKHUDOV $3% $+% SHULSKHUDOV )0& H[WHUQDO 0HP&WO $3% %XV PDWUL[ 6 -3 6 3.
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Functional overview STM32F427xx STM32F429xx The DMA can be used with the main peripherals: 3.9 • SPI and I2S • I2C • USART • General-purpose, basic and advanced-control timers TIMx • DAC • SDIO • Camera interface (DCMI) • ADC • SAI1. Flexible memory controller (FMC) All devices embed an FMC. It has four Chip Select outputs supporting the following modes: PCCard/Compact Flash, SDRAM/LPSDR SDRAM, SRAM, PSRAM, NOR Flash and NAND Flash.
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STM32F427xx STM32F429xx 3.11 Functional overview Chrom-ART Accelerator™ (DMA2D) The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit blitting, row data copy and pixel format conversion. It supports the following functions: • Rectangle filling with a fixed color • Rectangle copy • Rectangle copy with pixel format conversion • Rectangle composition with blending and pixel format conversion.
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Functional overview STM32F427xx STM32F429xx detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 180 MHz. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails).
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STM32F427xx STM32F429xx Functional overview reached, the option byte loading process starts, either to confirm or modify default BOR thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit.
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Functional overview STM32F427xx STM32F429xx Figure 7. PDR_ON control with internal reset OFF 9 '' 3'5 9 WLPH 5HVHW E\ RWKHU VRXUFH WKDQ SRZHU VXSSO\ VXSHUYLVRU 1567 3'5B21 3'5B21 WLPH 06 9 3.18 Voltage regulator The regulator has four operating modes: • • 3.18.1 Regulator ON – Main regulator mode (MR) – Low power regulator (LPR) – Power-down Regulator OFF Regulator ON On packages embedding the BYPASS_REG pin, the regulator is enabled by holding BYPASS_REG low.
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STM32F427xx STM32F429xx Functional overview The over-drive mode allows operating at a higher frequency than the normal mode for a given voltage scaling. – In Stop modes The MR can be configured in two ways during stop mode: MR operates in normal mode (default mode of MR in stop mode) MR operates in under-drive mode (reduced leakage mode). • LPR is used in the Stop modes: The LP regulator mode is configured by software when entering Stop mode.
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Functional overview STM32F427xx STM32F429xx In regulator OFF mode, the following features are no more supported: • PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power domain which is not reset by the NRST pin. • As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required.
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STM32F427xx STM32F429xx Functional overview Figure 9. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization 9'' 3'5 9 RU 9 9 0LQ 9 9&$3B 9&$3B WLPH 1567 WLPH DL I 1. This figure is valid whatever the internal reset mode (ON or OFF). Figure 10.
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Functional overview 3.18.3 STM32F427xx STM32F429xx Regulator ON/OFF and internal reset ON/OFF availability Table 4. Regulator ON/OFF and internal reset ON/OFF availability Package Regulator ON Regulator OFF LQFP100 Yes LQFP144, LQFP208 WLCSP143, LQFP176, UFBGA169, UFBGA176, TFBGA216 3.
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STM32F427xx STM32F429xx Functional overview Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date. Like backup SRAM, the RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or from the VBAT pin. 3.
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Functional overview 3.21 STM32F427xx STM32F429xx VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation.
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STM32F427xx STM32F429xx Functional overview Table 6.
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Functional overview 3.22.1 STM32F427xx STM32F429xx Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers.
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STM32F427xx STM32F429xx 3.22.4 Functional overview Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes.
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Functional overview STM32F427xx STM32F429xx communicate at speeds of up to 11.25 Mbit/s. The other available interfaces communicate at up to 5.62 bit/s. USART1, USART2, USART3 and USART6 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller. Table 8. USART feature comparison(1) USART name Standard Modem SPI LIN irDA features (RTS/CTS) master Smartcard (ISO 7816) Max.
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STM32F427xx STM32F429xx 3.26 Functional overview Inter-integrated sound (I2S) Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can be operated in master or slave mode, in full duplex and simplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported.
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Functional overview 3.30 STM32F427xx STM32F429xx Secure digital input/output interface (SDIO) An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory Card Specification Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit.
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STM32F427xx STM32F429xx Functional overview FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated for each CAN. 3.33 Universal serial bus on-the-go full-speed (OTG_FS) The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification.
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Functional overview 3.35 STM32F427xx STM32F429xx Digital camera interface (DCMI) The devices embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features: 3.
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STM32F427xx STM32F429xx 3.39 Functional overview Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally connected to the same input channel as VBAT, ADC1_IN18, which is used to convert the sensor output voltage into a digital value. When the temperature sensor and VBAT conversion are enabled at the same time, only VBAT conversion is performed.
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Functional overview 3.42 STM32F427xx STM32F429xx Embedded Trace Macrocell™ The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F42x through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel.
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STM32F427xx STM32F429xx 4 Pinouts and pin description Pinouts and pin description 6$$ 633 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 11.
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Pinouts and pin description STM32F427xx STM32F429xx Figure 12.
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STM32F427xx STM32F429xx Pinouts and pin description 6$$ 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 13.
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Pinouts and pin description STM32F427xx STM32F429xx 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! 6$$ 633 0) 0) 0) 0) 0) 0) 6 $$ Figure 14.
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0! 0! 0! 0( 0( 0( 0( 0! 633 6$$ 1. The above figure shows the package top view. 633 6$$ 0& 0& 0& 0& 0& 0( 0( .234 0# 0# 0# 0# 6$$ 633! 62%& 6$$! 0& 0& 0& 0% 0% 0% 0% 0% 6"!4 0) 0# 0# 0# 0) 0) 0) 633 6$$ 0& 0& 0& 0) 0) 0) Figure 15. STM32F42x LQFP208 pinout 0) 0) 0) 0) 6$$ 0$2?/.
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Pinouts and pin description STM32F427xx STM32F429xx Figure 16. STM32F42x UFBGA169 ballout 0) 0) 0% "//4 0" 0' 0$ 0$ 0# 0! 0) 0) 0% 0) 0% 0" 0" 0' 0$ 0$ 0# 0! 0) 0) 0% 0% 0$2 ?/.
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STM32F427xx STM32F429xx Pinouts and pin description Figure 17. STM32F42x UFBGA176 ballout ! 0% 0% " 0% # 0% 0% 0" 0" 0' 0' 0" 0% 0% 0" 0" 0" 0' 0' 6"!4 0) 0) 0) 6$$ 0$2?/. 6$$ $ 0# 0) 0) 0) 633 633 % 0# 0& 0) 0) & 0# 633 6$$ 0( 633 633 633 633 ' 0( 633 6$$ 0( 633 633 633 ( 0( 0& 0& 0( 633 633 * .
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Pinouts and pin description STM32F427xx STM32F429xx Figure 18. STM32F42x TFBGA216 ballout ! 0% 0% 0% 0' 0% 0% 0" 0" 0" 0" 0$ " 0% 0% 0' 0" 0" 0" 0' 0' 0* 0* # 6"!4 0) 0) 0+ 0+ 0+ 0' 0' 0* $ 0# 0& 0) 0) 0) 0) 0+ 0+ % 0# 0& 0) 0) 0$2? /. "//4 6$$ & 0# 633 0) 6$$ 6$$ 633 633 ' 0( 0& 0) 0) 6$$ ( 0( 0& 0) 0( * .
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STM32F427xx STM32F429xx Pinouts and pin description Table 9. Legend/abbreviations used in the pinout table Name Pin name Abbreviation Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O TTa 3.
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Pinouts and pin description STM32F427xx STM32F429xx Table 10.
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STM32F427xx STM32F429xx Pinouts and pin description Table 10.
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Pinouts and pin description STM32F427xx STM32F429xx Table 10.
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STM32F427xx STM32F429xx Pinouts and pin description Table 10.
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Pinouts and pin description STM32F427xx STM32F429xx Table 10.
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STM32F427xx STM32F429xx Pinouts and pin description Table 10.
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Pinouts and pin description STM32F427xx STM32F429xx Table 10.
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STM32F427xx STM32F429xx Pinouts and pin description Table 10.
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Pinouts and pin description STM32F427xx STM32F429xx Table 10.
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STM32F427xx STM32F429xx Pinouts and pin description Table 10.
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Pinouts and pin description STM32F427xx STM32F429xx Table 10.
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STM32F427xx STM32F429xx Pinouts and pin description Table 10.
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Pinouts and pin description STM32F427xx STM32F429xx Table 10.
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STM32F427xx STM32F429xx Pinouts and pin description Table 10.
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Pinouts and pin description STM32F427xx STM32F429xx Table 10.
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STM32F427xx STM32F429xx Pinouts and pin description Table 10.
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Pinouts and pin description STM32F427xx STM32F429xx Table 10.
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STM32F427xx STM32F429xx Pinouts and pin description 4. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F4xx reference manual, available from the STMicroelectronics website: www.st.com. 5.
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Pinouts and pin description STM32F427xx STM32F429xx Table 11. FMC pin definition 72/239 Downloaded from Arrow.com.
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STM32F427xx STM32F429xx Pinouts and pin description Table 11.
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Pinouts and pin description STM32F427xx STM32F429xx Table 11. FMC pin definition (continued) 74/239 Downloaded from Arrow.com.
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Memory mapping 5 STM32F427xx STM32F429xx Memory mapping The memory map is shown in Figure 19. Figure 19. Memory map [)))) )))) 5HVHUYHG [( [)))) )))) &RUWH[ 0 LQWHUQDO SHULSKHUDOV [( [( ) )))) $+% [ ['))) )))) 5HVHUYHG [ & [ ))) )))) [ %)) $+% 0E\WH %ORFN &RUWH[ 0 ,QWHUQDO SHULSKHUDOV 5HVHUYHG [ [ [ ))) )))) [ )))) [( ['))) )))) 0E\WH %ORFN )0& [' [&))) )))) $+% 0E\
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STM32F427xx STM32F429xx Memory mapping Table 13.
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Memory mapping STM32F427xx STM32F429xx Table 13.
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STM32F427xx STM32F429xx Memory mapping Table 13.
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Memory mapping STM32F427xx STM32F429xx Table 13. STM32F427xx and STM32F429xx register boundary addresses (continued) Bus APB1 90/239 Downloaded from Arrow.com.
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STM32F427xx STM32F429xx 6 6.1 Electrical characteristics Electrical characteristics Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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Electrical characteristics 6.1.6 STM32F427xx STM32F429xx Power supply scheme Figure 22. Power supply scheme 9%$7 9%$7 WR 9 *3,2V ,1 9&$3B 9&$3B î ) 9'' î Q) î ) 966 /HYHO VKLIWHU 287 9'' %DFNXS FLUFXLWU\ 26& . 57& :DNHXS ORJLF %DFNXS UHJLVWHUV EDFNXS 5$0 3RZHU VZLWFK ,2 /RJLF .HUQHO ORJLF &38 GLJLWDO 5$0 9ROWDJH UHJXODWRU )ODVK PHPRU\ %<3$66B5(* 3'5B21 9'' 9''$ 95() Q) ) 5HVHW FRQWUROOHU Q) ) 95(
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STM32F427xx STM32F429xx 6.1.7 Electrical characteristics Current consumption measurement Figure 23. Current consumption measurement scheme ,''B9%$7 9%$7 ,'' 9'' 9''$ DL 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 14: Voltage characteristics, Table 15: Current characteristics, and Table 16: Thermal characteristics may cause permanent damage to the device.
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Electrical characteristics STM32F427xx STM32F429xx Table 15. Current characteristics Symbol Ratings Max.
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STM32F427xx STM32F429xx Electrical characteristics 6.3 Operating conditions 6.3.1 General operating conditions Table 17. General operating conditions Symbol Parameter Conditions(1) Power Scale 3 (VOS[1:0] bits in PWR_CR register = 0x01), Regulator ON, over-drive OFF fHCLK Internal AHB clock frequency - 120 - 144 - 168 - 168 - 180 - 42 Over-drive ON 0 - 45 Over-drive OFF 0 - 84 Over-drive ON 0 - 90 Standard operating voltage 1.7(2) - 3.
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Electrical characteristics STM32F427xx STM32F429xx Table 17. General operating conditions (continued) Symbol Input voltage on RST and FT pins(7) VIN Conditions(1) Parameter Min Typ Max 2 V ≤ VDD ≤ 3.6 V − 0.3 - 5.5 VDD ≤ 2 V − 0.3 - 5.2 − 0.3 - VDDA+ 0.
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STM32F427xx STM32F429xx Electrical characteristics Table 18. Limitations depending on the operating power supply range Maximum Flash Maximum HCLK memory access frequency vs Flash frequency with memory wait states no wait states (1)(2) (fFlashmax) Possible Flash memory operations Operating power supply range ADC operation VDD =1.7 to 2.1 V(3) Conversion time up to 1.2 Msps 20 MHz(4) 168 MHz with 8 wait No I/O states and over-drive compensation OFF 8-bit erase and program operations only VDD = 2.
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Electrical characteristics 6.3.3 STM32F427xx STM32F429xx Operating conditions at power-up / power-down (regulator ON) Subject to general operating conditions for TA. Table 20. Operating conditions at power-up / power-down (regulator ON) Symbol tVDD 6.3.4 Parameter Min Max VDD rise time rate 20 ∞ VDD fall time rate 20 ∞ Unit µs/V Operating conditions at power-up / power-down (regulator OFF) Subject to general operating conditions for TA. Table 21.
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STM32F427xx STM32F429xx 6.3.5 Electrical characteristics Reset and power control block characteristics The parameters given in Table 22 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 17. Table 22. reset and power control block characteristics Symbol Parameter Conditions Programmable voltage detector level selection VPVD Min Typ Max Unit PLS[2:0]=000 (rising edge) 2.09 2.14 2.19 V PLS[2:0]=000 (falling edge) 1.98 2.04 2.
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Electrical characteristics STM32F427xx STM32F429xx Table 22. reset and power control block characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit IRUSH(1) InRush current on voltage regulator poweron (POR or wakeup from Standby) - 160 200 mA ERUSH(1) InRush energy on voltage regulator power- VDD = 1.7 V, TA = 105 °C, IRUSH = 171 mA for 31 µs on (POR or wakeup from Standby) - - 5.4 µC 1. Guaranteed by design. 2.
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STM32F427xx STM32F429xx 6.3.7 Electrical characteristics Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 23: Current consumption measurement scheme.
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Electrical characteristics STM32F427xx STM32F429xx Table 24.
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STM32F427xx STM32F429xx Electrical characteristics Table 25.
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Electrical characteristics STM32F427xx STM32F429xx Table 26.
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STM32F427xx STM32F429xx Electrical characteristics Table 27. Typical and maximum current consumptions in Stop mode Max(1) Typ Symbol Parameter Unit TA = 25 °C TA = 25 °C TA = TA = 85 °C 105 °C 0.40 1.50 14.00 25.00 0.35 1.50 14.00 25.00 0.29 1.10 10.00 18.00 0.23 1.10 10.00 18.00 Flash memory in Deep power down mode, main regulator in under-drive mode, all oscillators OFF, no independent watchdog 0.19 0.50 6.00 9.
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Electrical characteristics STM32F427xx STM32F429xx Table 28. Typical and maximum current consumptions in Standby mode Typ(1) Symbol Parameter Backup SRAM OFF, lowSupply current speed oscillator (LSE) and RTC ON IDD_STBY in Standby mode Backup SRAM ON, RTC and LSE OFF Backup SRAM OFF, RTC and LSE OFF TA = 25 °C TA = 25 °C Conditions Backup SRAM ON, low-speed oscillator (LSE) and RTC ON Max(2) TA = 85 °C TA = 105 °C VDD = 1.7 V VDD= 2.4 V VDD = 3.3 V 2.80 3.00 3.60 7.00 19.00 36.00 2.
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STM32F427xx STM32F429xx Electrical characteristics Figure 25. Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF) )$$?6"!4 ! 6 6 6 6 6 6 6 6 6 # # # # # 4EMPERATURE -3 6 Figure 26.
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Electrical characteristics STM32F427xx STM32F429xx Additional current consumption The MCU is placed under the following conditions: • All I/O pins are configured in analog mode. • The Flash memory access time is adjusted to fHCLK frequency. • The voltage scaling is adjusted to fHCLK frequency as follows: – Scale 3 for fHCLK ≤ 120 MHz, – Scale 2 for 120 MHz < fHCLK ≤ 144 MHz – Scale 1 for 144 MHz < fHCLK ≤ 180 MHz. The over-drive is only ON at 180 MHz.
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STM32F427xx STM32F429xx Table 31. Electrical characteristics Typical current consumption in Run mode, code with data processing running from Flash memory, regulator OFF (ART accelerator enabled except prefetch)(1) Symbol Parameter Conditions All Peripherals enabled IDD12 / IDD Supply current in RUN mode from V12 and VDD supply All Peripherals disabled fHCLK (MHz) VDD=3.3 V VDD=1.7 V Unit IDD12 IDD IDD12 IDD 168 77.8 1.3 76.8 1.0 150 70.8 1.3 69.8 1.0 144 64.5 1.3 63.6 1.
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Electrical characteristics STM32F427xx STM32F429xx Table 32. Typical current consumption in Sleep mode, regulator ON, VDD=1.7 V(1) Symbol Parameter Conditions All Peripherals enabled IDD Supply current in Sleep mode from VDD supply All Peripherals disabled fHCLK (MHz) Typ 168 65.5 150 55.5 144 53.5 120 39.0 90 31.6 60 21.7 30 9.8 25 8.8 168 15.7 150 13.7 144 12.7 120 9.7 90 7.7 60 5.7 30 4.7 25 2.8 Unit mA 1.
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STM32F427xx STM32F429xx Electrical characteristics Table 33. Tyical current consumption in Sleep mode, regulator OFF(1) VDD=3.3 V Symbol Parameter Conditions fHCLK (MHz) All Peripherals enabled IDD12/IDD Supply current in Sleep mode from V12 and VDD supply All Peripherals disabled VDD=1.7 V IDD12 IDD IDD12 IDD 180 61.5 1.4 - - 168 59.4 1.3 59.4 1.0 150 53.9 1.3 53.9 1.0 144 49.0 1.3 49.0 1.0 120 38.0 1.2 38.0 0.9 90 29.3 1.4 29.3 1.1 60 20.2 1.2 20.2 0.
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Electrical characteristics STM32F427xx STM32F429xx I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 56: I/O static characteristics.
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STM32F427xx STM32F429xx Electrical characteristics Table 34. Switching output I/O current consumption(1) I/O toggling Symbol Parameter Conditions VDD = 3.3 V C= CINT(2) IDDIO I/O switching Current VDD = 3.3 V CEXT = 0 pF C = CINT + CEXT + CS VDD = 3.3 V CEXT = 10 pF C = CINT + CEXT + CS IDDIO I/O switching Current VDD = 3.3 V CEXT = 22 pF C = CINT + CEXT + CS VDD = 3.3 V CEXT = 33 pF C = CINT + Cext + CS frequency (fsw) Typ 2 MHz 0.0 8 MHz 0.2 25 MHz 0.6 50 MHz 1.1 60 MHz 1.
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Electrical characteristics STM32F427xx STM32F429xx On-chip peripheral current consumption The MCU is placed under the following conditions: • At startup, all I/O pins are in analog input configuration. • All peripherals are disabled unless otherwise mentioned. • I/O compensation cell enabled. • The ART accelerator is ON. • Scale 1 mode selected, internal digital voltage V12 = 1.32 V. • HCLK is the system clock. fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2.
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STM32F427xx STM32F429xx Electrical characteristics Table 35. Peripheral current consumption (continued) IDD( Typ)(1) Peripheral AHB2 (up to 180 MHz) AHB3 (up to 180 MHz) Scale 2 Scale 3 OTG_FS 25.67 26.67 23.58 DCMI 3.72 3.40 3.00 RNG 2.28 2.36 2.17 FMC 21.39 19.79 17.50 µA/MHz 14.06 13.19 11.75 µA/MHz TIM2 17.56 16.42 14.47 TIM3 14.22 13.36 11.80 TIM4 14.89 13.64 12.13 TIM5 17.33 16.42 14.47 TIM6 2.89 2.53 2.47 TIM7 3.11 2.81 2.47 TIM12 7.33 6.97 6.
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Electrical characteristics STM32F427xx STM32F429xx Table 35. Peripheral current consumption (continued) IDD( Typ)(1) Peripheral APB2 (up to 90 MHz) Unit Scale 1 Scale 2 Scale 3 SDIO 8.11 8.75 7.83 TIM1 17.11 15.97 14.17 TIM8 17.33 16.11 14.33 TIM9 7.22 6.67 6.00 TIM10 4.56 4.31 3.83 TIM11 4.78 4.44 4.00 ADC1(5) 4.67 4.31 3.83 ADC2(5) 4.78 4.44 4.00 ADC3(5) 4.56 4.17 3.67 SPI1 1.44 1.39 1.17 USART1 4.00 3.75 3.33 USART6 4.00 3.75 3.33 SPI4 1.44 1.
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STM32F427xx STM32F429xx 6.3.8 Electrical characteristics Wakeup time from low-power modes The wakeup times given in Table 36 are measured starting from the wakeup event trigger up to the first instruction executed by the CPU: • For Stop or Sleep modes: the wakeup event is WFE. • WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes. All timings are derived from tests performed under ambient temperature and VDD=3.3 V. Table 36.
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Electrical characteristics 6.3.9 STM32F427xx STM32F429xx External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 56: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 27.
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STM32F427xx STM32F429xx Electrical characteristics Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 56: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 28.
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Electrical characteristics STM32F427xx STM32F429xx Figure 28. Low-speed external clock source AC timing diagram 9/6(+ 9/6(/ WU /6( WI /6( W W: /6( W: /6( 7/6( I/6(BH[W ([WHUQDO FORFN VRXUFH ,/ 26& B,1 670 ) DL High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator.
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STM32F427xx STM32F429xx Electrical characteristics For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 29). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2.
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Electrical characteristics STM32F427xx STM32F429xx Figure 30. Typical application with a 32.768 kHz crystal 5HVRQDWRU ZLWK LQWHJUDWHG FDSDFLWRUV &/ I/6( 26& B,1 %LDV 5) FRQWUROOHG JDLQ N+ ] UHVRQDWRU 26& B28 7 &/ 670 ) DL 6.3.10 Internal clock source characteristics The parameters given in Table 41 and Table 42 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 17. High-speed internal (HSI) RC oscillator Table 41.
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STM32F427xx STM32F429xx Electrical characteristics Figure 31. ACCHSI accuracy versus temperature $&&+6, 7$ & 0LQ 0D[ 7\SLFDO 06Y 9 1. Guaranteed by characterization results. Low-speed internal (LSI) RC oscillator Table 42. LSI oscillator characteristics (1) Symbol fLSI(2) tsu(LSI) Parameter Frequency Min Typ Max Unit 17 32 47 kHz (3) LSI oscillator startup time - 15 40 µs (3) LSI oscillator power consumption - 0.4 0.
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Electrical characteristics STM32F427xx STM32F429xx Figure 32. ACCLSI versus temperature MAX AVG MIN .ORMALIZED DEVIATI ON 4EMPERAT URE # -3 6 6.3.11 PLL characteristics The parameters given in Table 43 and Table 44 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 17. Table 43.
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STM32F427xx STM32F429xx Electrical characteristics Table 43.
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Electrical characteristics STM32F427xx STM32F429xx Table 44. PLLI2S (audio PLL) characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit IDD(PLLI2S)(4) PLLI2S power consumption on VDD VCO freq = 100 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLLI2S)(4) PLLI2S power consumption on VDDA VCO freq = 100 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA 1. Take care of using the appropriate division factor M to have the specified PLL input clock values. 2.
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STM32F427xx STM32F429xx 6.3.12 Electrical characteristics PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 52: EMI characteristics). It is available only on the main PLL. Table 46. SSCG parameters constraint Symbol Parameter Min Typ Max(1) Unit fMod Modulation frequency - - 10 KHz md Peak modulation depth 0.25 - 2 % MODEPER * INCSTEP - - 215 −1 - 1.
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Electrical characteristics STM32F427xx STM32F429xx Figure 33 and Figure 34 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 33. PLL output clock waveforms in center spread mode &REQUENCY 0,,?/54 MD & MD TMODE 4IME XTMODE AI Figure 34. PLL output clock waveforms in down spread mode )UHTXHQF\ 3//B287 ) [PG WPRGH [WPRGH 7LPH DL E 128/239 Downloaded fr
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STM32F427xx STM32F429xx 6.3.13 Electrical characteristics Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. The devices are shipped to customers with the Flash memory erased. Table 47. Flash memory characteristics Symbol IDD Parameter Supply current Conditions Min Typ Max Write / Erase 8-bit mode, VDD = 1.7 V - 5 - Write / Erase 16-bit mode, VDD = 2.1 V - 8 - Write / Erase 32-bit mode, VDD = 3.
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Electrical characteristics STM32F427xx STM32F429xx Table 48. Flash memory programming (continued) Symbol tBE Vprog Parameter Bank erase time Programming voltage Conditions Min(1) Typ Max(1) Unit Program/erase parallelism (PSIZE) = x 8 - 16 32 Program/erase parallelism (PSIZE) = x 16 - 11 22 Program/erase parallelism (PSIZE) = x 32 - 8 16 32-bit program operation 2.7 - 3.6 V 16-bit program operation 2.1 - 3.6 V 8-bit program operation 1.7 - 3.6 V s 1.
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STM32F427xx STM32F429xx Electrical characteristics Table 50. Flash memory endurance and data retention Value Symbol NEND tRET Parameter Endurance Data retention Conditions Min(1) TA = –40 to +85 °C (6 suffix versions) TA = –40 to +105 °C (7 suffix versions) 10 1 kcycle(2) at TA = 85 °C 30 1 kcycle (2) 10 kcycles at TA = 105 °C 10 (2) 20 at TA = 55 °C Unit kcycles Years 1. Guaranteed by characterization results. 2. Cycling performed over the whole temperature range. 6.3.
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Electrical characteristics STM32F427xx STM32F429xx Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.
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STM32F427xx STM32F429xx 6.3.15 Electrical characteristics Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination.
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Electrical characteristics 6.3.16 STM32F427xx STM32F429xx I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.
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STM32F427xx STM32F429xx 6.3.17 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 56: I/O static characteristics are derived from tests performed under the conditions summarized in Table 17. All I/Os are CMOS and TTL compliant. Table 56. I/O static characteristics Symbol Parameter Conditions 1.7 V≤VDD≤3.6 V BOOT0 I/O input low level voltage FT, TTa and NRST I/O input high level voltage(5) - 1.
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Electrical characteristics STM32F427xx STM32F429xx Table 56.
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STM32F427xx STM32F429xx Electrical characteristics Figure 35.
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Electrical characteristics STM32F427xx STM32F429xx Output voltage levels Unless otherwise specified, the parameters given in Table 57 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 17. All I/Os are CMOS and TTL compliant. Table 57.
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STM32F427xx STM32F429xx Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 36 and Table 58, respectively. Unless otherwise specified, the parameters given in Table 58 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 17. Table 58.
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Electrical characteristics STM32F427xx STM32F429xx Table 58. I/O AC characteristics(1)(2) (continued) OSPEEDRy [1:0] bit value(1) Symbol fmax(IO)out Parameter Conditions Maximum frequency(3) 11 tf(IO)out/ tr(IO)out - tEXTIpw Output high to low level fall time and output low to high level rise time Min Typ Max CL = 30 pF, VDD ≥ 2.7 V - - 100(4) CL = 30 pF, VDD ≥ 1.8 V - - 50 CL = 30 pF, VDD ≥ 1.7 V - - 42.5 CL = 10 pF, VDD≥ 2.7 V - - 180(4) CL = 10 pF, VDD ≥ 1.
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STM32F427xx STM32F429xx 6.3.18 Electrical characteristics NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 56: I/O static characteristics). Unless otherwise specified, the parameters given in Table 59 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 17. Table 59.
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Electrical characteristics 6.3.19 STM32F427xx STM32F429xx TIM timer characteristics The parameters given in Table 60 are guaranteed by design. Refer to Section 6.3.17: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 60.
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STM32F427xx STM32F429xx Electrical characteristics Table 61. I2C analog filter characteristics(1) Symbol tAF Parameter Maximum pulse width of spikes that are suppressed by the analog filter Min Max Unit 50(2) 260(3) ns 1. Guaranteed by design. 2. Spikes with widths below tAF(min) are filtered. 3.
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Electrical characteristics STM32F427xx STM32F429xx Table 62. SPI dynamic characteristics(1) (continued) Symbol Parameter tw(SCKH) SCK high and low time tw(SCKL) Conditions Min Typ Max Master mode, SPI presc = 2, 2.7 V≤VDD≤3.6 V TPCLK − 0.5 TPCLK TPCLK+0.5 Master mode, SPI presc = 2, 1.7 V≤VDD≤3.
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STM32F427xx STM32F429xx Electrical characteristics Figure 38. SPI timing diagram - slave mode and CPHA = 0 Figure 39. SPI timing diagram - slave mode and CPHA = 1 166 LQSXW 6&. LQSXW W68 166 &3+$ &32/ &3+$ &32/ WZ 6&.+ WZ 6&./ WK 62 WY 62 WD 62 0,62 287387 06% 287 %,7 287 WU 6&. WI 6&. WGLV 62 /6% 287 WK 6, WVX 6, 026, ,1387 WK 166 WF 6&. 06% ,1 %,7 ,1 /6% ,1 DL E DocID024030 Rev 10 145/239 198 Downloaded from Arrow.com.
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Electrical characteristics STM32F427xx STM32F429xx Figure 40. SPI timing diagram - master mode +LJK 166 LQSXW 6&. 2XWSXW &3+$ &32/ 6&. 2XWSXW WF 6&. &3+$ &32/ &3+$ &32/ &3+$ &32/ WVX 0, 0,62 ,13 87 WZ 6&.+ WZ 6&./ WU 6&. WI 6&. %,7 ,1 06% ,1 /6% ,1 WK 0, 026, 287387 06% 287 WY 02 % , 7 287 /6% 287 WK 02 DL F 146/239 Downloaded from Arrow.com.
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STM32F427xx STM32F429xx Electrical characteristics I2S interface characteristics Unless otherwise specified, the parameters given in Table 63 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.
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Electrical characteristics STM32F427xx STM32F429xx Figure 41. I2S slave timing diagram (Philips protocol)(1) 1. .LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 42. I2S master timing diagram (Philips protocol)(1) 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 148/239 Downloaded from Arrow.com.
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STM32F427xx STM32F429xx Electrical characteristics SAI characteristics Unless otherwise specified, the parameters given in Table 64 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C=30 pF • Measurement points are performed at CMOS levels: 0.5VDD Refer to Section 6.3.
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Electrical characteristics STM32F427xx STM32F429xx Figure 43. SAI master timing waveforms F3#+ 3!)?3#+?8 TH &3 3!)?&3?8 OUTPUT TV &3 TH 3$?-4 TV 3$?-4 3!)?3$?8 TRANSMIT 3LOT N 3LOT N TSU 3$?-2 TH 3$?-2 3!)?3$?8 RECEIVE 3LOT N -3 6 Figure 44. SAI slave timing waveforms F3#+ 3!)?3#+?8 TW #+(?8 3!)?&3?8 INPUT TW #+,?8 TH &3 TSU &3 3!)?3$?8 TRANSMIT 3LOT N TSU 3$?32 3!)?3$?8 RECEIVE TH 3$?34 TV 3$?34 3LOT N TH 3$?32 3LOT N -3 6 150/239 Downloaded from Arrow.com.
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STM32F427xx STM32F429xx Electrical characteristics USB OTG full speed (FS) characteristics This interface is present in both the USB OTG HS and USB OTG FS controllers. Table 65. USB OTG full speed startup time Symbol tSTARTUP(1) Parameter Max Unit USB OTG full speed transceiver startup time 1 µs 1. Guaranteed by design. Table 66. USB OTG full speed DC electrical characteristics Symbol VDD Input levels Parameter Conditions USB OTG full speed transceiver operating voltage Min.(1) Typ. Max.
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Electrical characteristics STM32F427xx STM32F429xx Figure 45. USB OTG full speed timings: definition of data signal rise and fall time &URVV RYHU SRLQWV 'LIIHUHQWLDO GDWD OLQHV 9&56 966 WI WU DL E Table 67. USB OTG full speed electrical characteristics(1) Driver characteristics Symbol tr tf trfm Parameter Rise time(2) Fall time(2) Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 110 % 1.3 2.
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STM32F427xx STM32F429xx Electrical characteristics Table 69. USB HS clock timing parameters(1) Symbol Parameter Min Typ Max Unit fHCLK value to guarantee proper operation of USB HS interface 30 - - MHz FSTART_8BIT Frequency (first transition) 54 60 66 MHz FSTEADY Frequency (steady state) ±500 ppm 59.97 60 60.03 MHz DSTART_8BIT Duty cycle (first transition) 40 50 60 % DSTEADY Duty cycle (steady state) ±500 ppm 49.975 50 50.
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Electrical characteristics STM32F427xx STM32F429xx Table 70. Dynamic characteristics: USB ULPI(1) Symbol Parameter Conditions Min. Typ. Max. tSC Control in (ULPI_DIR, ULPI_NXT) setup time 2 - - tHC Control in (ULPI_DIR, ULPI_NXT) hold time 0.5 - - tSD Data in setup time 1.5 - - tHD Data in hold time 2 - - 2.7 V < VDD < 3.6 V, CL = 15 pF and OSPEEDRy[1:0] = 11 - 9 9.5 2.7 V < VDD < 3.6 V, CL = 20 pF and OSPEEDRy[1:0] = 10 - 1.7 V < VDD < 3.
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STM32F427xx STM32F429xx Electrical characteristics Ethernet characteristics Unless otherwise specified, the parameters given in Table 71, Table 72 and Table 73 for SMI, RMII and MII are derived from tests performed under the ambient temperature, fHCLK frequency summarized in Table 17 with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF for 2.7 V < VDD < 3.6 V • Capacitive load C = 20 pF for 1.71 V < VDD < 3.
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Electrical characteristics STM32F427xx STM32F429xx Table 72 gives the list of Ethernet MAC signals for the RMII and Figure 48 shows the corresponding timing diagram. Figure 48. Ethernet RMII timing diagram 50,,B5()B&/. WG 7;(1 WG 7;' 50,,B7;B(1 50,,B7;'> @ WVX 5;' WVX &56 WLK 5;' WLK &56 50,,B5;'> @ 50,,B&56B'9 DL E Table 72.
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STM32F427xx STM32F429xx Electrical characteristics Figure 49. Ethernet MII timing diagram 0,,B5;B&/. WVX 5;' WVX (5 WVX '9 WLK 5;' WLK (5 WLK '9 0,,B5;'> @ 0,,B5;B'9 0,,B5;B(5 0,,B7;B&/. WG 7;(1 WG 7;' 0,,B7;B(1 0,,B7;'> @ AI B Table 73.
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Electrical characteristics 6.3.21 STM32F427xx STM32F429xx 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 74 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 17. Table 74. ADC characteristics Symbol Parameter VDDA Power supply VREF+ Positive reference voltage VREF- Negative reference voltage Conditions Typ Max (1) 1.7 - 3.6 1.7(1) - VDDA - 0 - 0.
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STM32F427xx STM32F429xx Electrical characteristics Table 74. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit 12-bit resolution Single ADC - - 2 Msps 12-bit resolution Interleave Dual ADC mode - - 3.
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Electrical characteristics a Table 76. ADC static accuracy at fADC = 30 MHz Symbol ET STM32F427xx STM32F429xx Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fADC = 30 MHz, RAIN < 10 kΩ, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V, VDDA − VREF < 1.2 V Typ Max(1) ±2 ±5 ±1.5 ±2.5 ±1.5 ±3 ±1 ±2 ±1.5 ±3 Unit LSB 1. Guaranteed by characterization results. Table 77.
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STM32F427xx STM32F429xx Note: Electrical characteristics ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.
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Electrical characteristics STM32F427xx STM32F429xx Figure 51. Typical connection diagram using the ADC 670 ) 9'' 5$,1 9$,1 6DPSOH DQG KROG $'& FRQYHUWHU 97 9 5$'& $,1[ &SDUDVLWLF 97 9 ,/ $ ELW FRQYHUWHU & $'& DL 1. Refer to Table 74 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy.
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STM32F427xx STM32F429xx Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 52 or Figure 53, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 52. Power supply and reference decoupling (VREF+ not connected to VDDA) 670 ) 95() ) Q) 9''$ ) Q) 966$ 95() DL E 1.
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Electrical characteristics STM32F427xx STM32F429xx Figure 53. Power supply and reference decoupling (VREF+ connected to VDDA) 670 ) 95() 9''$ ) Q) 95() 966$ DL F 1. VREF+ and VREF– inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144, and LQFP176. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. 6.3.22 Temperature sensor characteristics Table 80.
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STM32F427xx STM32F429xx 6.3.23 Electrical characteristics VBAT monitoring characteristics Table 82. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit KΩ R Resistor bridge for VBAT - 50 - Q Ratio on VBAT measurement - 4 - Error on Q –1 - +1 % ADC sampling time when reading the VBAT 1 mV accuracy 5 - - µs Er (1) TS_vbat(2)(2) 1. Guaranteed by design. 2. Shortest sampling time can be determined in the application by multiple iterations. 6.3.
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Electrical characteristics 6.3.25 STM32F427xx STM32F429xx DAC electrical characteristics Table 85. DAC characteristics Symbol Parameter Conditions Min Typ VDDA Analog supply voltage - 1.7(1) - 3.6 V - VREF+ Reference supply voltage - 1.7(1) - 3.
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STM32F427xx STM32F429xx Electrical characteristics Table 85. DAC characteristics (continued) Symbol Parameter DAC DC VDDA IDDA(4) current consumption in quiescent mode(3) Conditions Min Typ Max Unit Comments - - 280 380 µA 625 With no load, worst code (0xF1C) at VREF+ = 3.6 V in µA terms of DC consumption on the inputs With no load, middle code (0x800) on the inputs - - 475 - - - - - - ±2 LSB Given for the DAC in 12-bit configuration.
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Electrical characteristics STM32F427xx STM32F429xx Table 85. DAC characteristics (continued) Symbol Conditions Min Typ Wakeup time from off tWAKEUP( state (Setting the ENx 4) bit in the DAC Control register) - - 6.5 10 CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ µs input code between lowest and highest possible ones. Power supply rejection ratio (to VDDA) (static DC measurement) - - –67 –40 dB No RLOAD, CLOAD = 50 pF PSRR+ (2) Parameter Max Unit Comments 1. VDDA minimum value of 1.
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STM32F427xx STM32F429xx 6.3.26 Electrical characteristics FMC characteristics Unless otherwise specified, the parameters given in Table 86 to Table 101 for the FMC interface are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 except at VDD range 1.7 to 2.1V where OSPEEDRy[1:0] = 11 • Measurement points are done at CMOS levels: 0.
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Electrical characteristics STM32F427xx STM32F429xx Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms TW .% &-#?.% TV ./%?.% T W ./% T H .%?./% &-#?./% &-#?.7% TV !?.% &-#?!; = T H !?./% !DDRESS TV ",?.% T H ",?./% &-#?.",; = T H $ATA?.% T SU $ATA?./% TH $ATA?./% T SU $ATA?.% $ATA &-#?$; = T V .!$6?.% TW .!$6 &-#?.!$6 &-#?.7!)4 TH .%?.7!)4 TSU .7!)4?.% -3 6 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. Table 86.
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STM32F427xx STM32F429xx Electrical characteristics Table 86. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) (continued) Symbol Parameter Min Max Unit th(Data_NOE) Data hold time after FMC_NOE high 0 - ns th(Data_NE) Data hold time after FMC_NEx high 0 - ns tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0 ns FMC_NADV low time - THCLK +1 ns tw(NADV) 1. CL = 30 pF. 2. Guaranteed by characterization results. Table 87.
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Electrical characteristics STM32F427xx STM32F429xx Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms TW .% &-#?.%X &-#?./% TV .7%?.% TW .7% T H .%?.7% &-#?.7% TV !?.% &-#?!; = TH !?.7% !DDRESS TV ",?.% &-#?.",; = TH ",?.7% .", TV $ATA?.% TH $ATA?.7% $ATA &-#?$; = T V .!$6?.% &-#?.!$6 TW .!$6 &-#?.7!)4 TH .%?.7!)4 TSU .7!)4?.% -3 6 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. Table 88.
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STM32F427xx STM32F429xx Electrical characteristics Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR write NWAIT timings(1)(2) Symbol Parameter Min Max Unit FMC_NE low time 8THCLK+1 8THCLK+2 ns FMC_NWE low time 6THCLK − 1 6THCLK+2 ns tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK+1.5 - ns th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid tw(NE) tw(NWE) 4THCLK+1 ns 1. CL = 30 pF. 2. Guaranteed by characterization results. Figure 57.
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Electrical characteristics STM32F427xx STM32F429xx Table 90. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Symbol tw(NE) tv(NOE_NE) ttw(NOE) th(NE_NOE) tv(A_NE) tv(NADV_NE) tw(NADV) Parameter Min Max Unit 3THCLK − 1 3THCLK+0.5 ns 2THCLK − 0.5 2THCLK ns THCLK − 1 THCLK+1 ns FMC_NOE high to FMC_NE high hold time 1 - ns FMC_NEx low to FMC_A valid - 2 ns FMC_NEx low to FMC_NADV low 0 2 ns THCLK − 0.5 THCLK+0.
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STM32F427xx STM32F429xx Electrical characteristics Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms TW .% &-#? .%X &-#?./% TW .7% TV .7%?.% T H .%?.7% &-#?.7% TH !?.7% TV !?.% &-#? !; = !DDRESS TV ",?.% &-#? .",; = TH ",?.7% .", T V !?.% T V $ATA?.!$6 !DDRESS &-#? !$; = TH $ATA?.7% $ATA TH !$?.!$6 T V .!$6?.% TW .!$6 &-#?.!$6 &-#?.7!)4 TH .%?.7!)4 TSU .7!)4?.% -3 6 Table 92.
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Electrical characteristics STM32F427xx STM32F429xx Table 93. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2) Symbol tw(NE) tw(NWE) Parameter Min Max Unit FMC_NE low time 9THCLK 9THCLK+0.5 ns FMC_NWE low time 7THCLK 7THCLK+2 ns 6THCLK+1.5 - ns 4THCLK–1 - ns tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 1. CL = 30 pF. 2. Guaranteed by characterization results.
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STM32F427xx STM32F429xx Electrical characteristics Figure 59. Synchronous multiplexed NOR/PSRAM read timings "53452. TW #,+ TW #,+ &-#?#,+ $ATA LATENCY TD #,+, .%X, &-#?.%X T D #,+, .!$6, TD #,+( .%X( TD #,+, .!$6( &-#?.!$6 TD #,+, !6 TD #,+( !)6 &-#?!; = TD #,+, ./%, TD #,+( ./%( &-#?./% T D #,+, !$6 &-#?!$; = TD #,+, !$)6 TSU !$6 #,+( !$; = TH #,+( !$6 TSU !$6 #,+( $ TSU .7!)46 #,+( &-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( &-#?.
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Electrical characteristics STM32F427xx STM32F429xx Table 94. Synchronous multiplexed NOR/PSRAM read timings(1)(2) (continued) Symbol Parameter Min Max Unit tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 5 - ns th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 0 - ns tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 4 - ns th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 0 - ns 1. CL = 30 pF. 2. Guaranteed by characterization results. Figure 60.
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STM32F427xx STM32F429xx Electrical characteristics Table 95. Synchronous multiplexed PSRAM write timings(1)(2) Symbol Min Max Unit 2THCLK − 1 - ns - 1.5 ns THCLK - ns td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0 ns td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - ns - 0 ns THCLK - ns - 0 ns THCLK −0.5 - ns tw(CLK) Parameter FMC_CLK period, VDD range= 2.7 to 3.6 V td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..
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Electrical characteristics STM32F427xx STM32F429xx Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings TW #,+ TW #,+ &-#?#,+ TD #,+, .%X, TD #,+( .%X( $ATA LATENCY &-#?.%X TD #,+, .!$6, TD #,+, .!$6( &-#?.!$6 TD #,+( !)6 TD #,+, !6 &-#?!; = TD #,+, ./%, TD #,+( ./%( &-#?./% TSU $6 #,+( TH #,+( $6 TSU $6 #,+( &-#?$; = TH #,+( $6 $ &-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( TH #,+( .7!)46 TSU .7!)46 #,+( &-#?.7!)4 7!)4#&' B 7!)40/, B $ TSU .
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STM32F427xx STM32F429xx Electrical characteristics Table 96. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) (continued) Symbol Parameter th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high th(CLKH- Max Unit 0 - ns 4 FMC_NWAIT valid after FMC_CLK high NWAIT) Min 0 1. CL = 30 pF. 2. Guaranteed by characterization results. Figure 62. Synchronous non-multiplexed PSRAM write timings TW #,+ TW #,+ &-#?#,+ TD #,+, .%X, TD #,+( .
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Electrical characteristics STM32F427xx STM32F429xx Table 97. Synchronous non-multiplexed PSRAM write timings(1)(2) (continued) Symbol td(CLKH-AIV) td(CLKL-NWEL) Parameter Min Max Unit FMC_CLK high to FMC_Ax invalid (x=16…25) 0 - ns FMC_CLK low to FMC_NWE low - 0 ns THCLK −0.5 - ns td(CLKH-NWEH) FMC_CLK high to FMC_NWE high td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 2.
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STM32F427xx STM32F429xx Electrical characteristics Figure 63. PC Card/CompactFlash controller waveforms for common memory read access &-#?.#% ? &-#?.#% ? TH .#%X !) TV .#%X ! &-#?!; = TH .#%X .2%' TH .#%X .)/2$ TH .#%X .)/72 TD .2%' .#%X TD .)/2$ .#%X &-#?.2%' &-#?.)/72 &-#?.)/2$ &-#?.7% TD .#% ? ./% &-#?./% TW ./% TSU $ ./% TH ./% $ &-#?$; = -3 6 1. FMC_NCE4_2 remains high (inactive during 8-bit access. Figure 64.
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Electrical characteristics STM32F427xx STM32F429xx Figure 65. PC Card/CompactFlash controller waveforms for attribute memory read access &-#?.#% ? TV .#% ? ! &-#?.#% ? TH .#% ? !) (IGH &-#?!; = &-#?.)/72 &-#?.)/2$ TD .2%' .#% ? TH .#% ? .2%' &-#?.2%' &-#?.7% TD .#% ? ./% TW ./% TD ./% .#% ? &-#?./% TSU $ ./% TH ./% $ &-#?$; = -3 6 1. Only data bits 0...7 are read (bits 8...15 are disregarded). 184/239 Downloaded from Arrow.com.
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STM32F427xx STM32F429xx Electrical characteristics Figure 66. PC Card/CompactFlash controller waveforms for attribute memory write access &-#?.#% ? &-#?.#% ? (IGH TV .#% ? ! TH .#% ? !) &-#?!; = &-#?.)/72 &-#?.)/2$ TD .2%' .#% ? TH .#% ? .2%' &-#?.2%' TD .#% ? .7% TW .7% &-#?.7% TD .7% .#% ? &-#?./% TV .7% $ &-#?$; = -3 6 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Figure 67. PC Card/CompactFlash controller waveforms for I/O space read access &-#?.
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Electrical characteristics STM32F427xx STM32F429xx Figure 68. PC Card/CompactFlash controller waveforms for I/O space write access &-#?.#% ? &-#?.#% ? TV .#%X ! TH .#% ? !) &-#?!; = &-#?.2%' &-#?.7% &-#?./% &-#?.)/2$ T D .#% ? .)/72 TW .)/72 &-#?.)/72 !44X(): TV .)/72 $ TH .)/72 $ &-#?$; = -3 6 Table 98.
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STM32F427xx STM32F429xx Electrical characteristics Table 99. Switching characteristics for PC Card/CF read and write cycles in I/O space(1)(2) Symbol Parameter tw(NIOWR) FMC_NIOWR low width tv(NIOWR-D) FMC_NIOWR low to FMC_D[15:0] valid th(NIOWR-D) FMC_NIOWR high to FMC_D[15:0] invalid Min Max Unit 8THCLK − 0.5 - ns - 0 ns 9THCLK − 2 - ns - 5THCLK ns 5THCLK - ns - 5THCLK ns 6THCLK+2 - ns 8THCLK − 0.5 8THCLK+0.
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Electrical characteristics STM32F427xx STM32F429xx Figure 69. NAND controller waveforms for read access &-#?.#%X !,% &-#?! #,% &-#?! &-#?.7% TD !,% ./% TH ./% !,% &-#?./% .2% TSU $ ./% TH ./% $ &-#?$; = -3 6 Figure 70. NAND controller waveforms for write access &-#?.#%X !,% &-#?! #,% &-#?! TH .7% !,% TD !,% .7% &-#?.7% &-#?./% .2% TV .7% $ TH .7% $ &-#?$; = -3 6 188/239 Downloaded from Arrow.com.
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STM32F427xx STM32F429xx Electrical characteristics Figure 71. NAND controller waveforms for common memory read access &-#?.#%X !,% &-#?! #,% &-#?! TH ./% !,% TD !,% ./% &-#?.7% TW ./% &-#?./% TSU $ ./% TH ./% $ &-#?$; = -3 6 Figure 72. NAND controller waveforms for common memory write access &-#?.#%X !,% &-#?! #,% &-#?! TD !,% ./% TW .7% TH ./% !,% &-#?.7% &-#?. /% TD $ .7% TV .7% $ TH .7% $ &-#?$; = -3 6 Table 100.
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Electrical characteristics STM32F427xx STM32F429xx Table 101. Switching characteristics for NAND Flash write cycles(1) Symbol tw(NWE) Parameter FMC_NWE low width Min Max Unit 4THCLK 4THCLK+1 ns 0 - ns tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 3THCLK − 1 - ns td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 5THCLK − 3 - ns - 3THCLK −0.
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STM32F427xx STM32F429xx Electrical characteristics Table 102. SDRAM read timings(1)(2) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2THCLK − 0.5 2THCLK+0.5 tsu(SDCLKH _Data) Data input setup time 2 - th(SDCLKH_Data) Data input hold time 0 - td(SDCLKL_Add) Address valid time - 1.5 td(SDCLKL- SDNE) Chip select valid time - 0.5 th(SDCLKL_SDNE) Chip select hold time 0 - td(SDCLKL_SDNRAS) SDNRAS valid time - 0.
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Electrical characteristics STM32F427xx STM32F429xx Figure 74. SDRAM write access waveforms &-#?3$#,+ TD 3$#,+,?!DD# TH 3$#,+,?!DD2 TD 3$#,+,?!DD2 &-#?!> @ 2OW N #OL #OL #OLI #OLN TH 3$#,+,?!DD# TH 3$#,+,?3.$% TD 3$#,+,?3.$% &-#?3$.%; = TH 3$#,+,?.2!3 TD 3$#,+,?.2!3 &-#?3$.2!3 TD 3$#,+,?.#!3 TH 3$#,+,?.#!3 TD 3$#,+,?.7% TH 3$#,+,?.7% &-#?3$.#!3 &-#?3$.7% TD 3$#,+,?$ATA &-#?$; = TD 3$#,+,?.", $ATA $ATA $ATAI $ATAN TH 3$#,+,?$ATA &-#?.
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STM32F427xx STM32F429xx Electrical characteristics Table 104. SDRAM write timings(1)(2) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2THCLK − 0.5 2THCLK+0.5 td(SDCLKL _Data) Data output valid time - 3.5 th(SDCLKL _Data) Data output hold time 0 - td(SDCLKL_Add) Address valid time - 1.5 td(SDCLKL_SDNWE) SDNWE valid time - 1 th(SDCLKL_SDNWE) SDNWE hold time 0 - td(SDCLKL_ SDNE) Chip select valid time - 0.
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Electrical characteristics 6.3.27 STM32F427xx STM32F429xx Camera interface (DCMI) timing specifications Unless otherwise specified, the parameters given in Table 106 for DCMI are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 17, with the following configuration: • DCMI_PIXCLK polarity: falling • DCMI_VSYNC and DCMI_HSYNC polarity: high • Data formats: 14 bits Table 106. DCMI characteristics Symbol Parameter Min Max - 0.
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STM32F427xx STM32F429xx 6.3.28 Electrical characteristics LCD-TFT controller (LTDC) characteristics Unless otherwise specified, the parameters given in Table 107 for LCD-TFT are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 17, with the following configuration: • LCD_CLK polarity: high • LCD_DE polarity : low • LCD_VSYNC and LCD_HSYNC polarity: high • Pixel formats: 24 bits Table 107.
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Electrical characteristics STM32F427xx STM32F429xx Figure 76. LCD-TFT horizontal timing diagram W&/. /&'B&/. /&'B96<1& WY +6<1& WY +6<1& /&'B+6<1& WK '( WY '( /&'B'( WY '$7$ /&'B5> @ /&'B*> @ /&'B%> @ 1JYFM 1JYFM 1JYFM / WK '$7$ +6<1& +RUL]RQWDO ZLGWK EDFN SRUFK $FWLYH ZLGWK +RUL]RQWDO EDFN SRUFK 2QH OLQH 06 9 Figure 77. LCD-TFT vertical timing diagram W&/. /&'B&/.
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STM32F427xx STM32F429xx 6.3.29 Electrical characteristics SD/SDIO MMC card host interface (SDIO) characteristics Unless otherwise specified, the parameters given in Table 108 for the SDIO/MMC interface are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.
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Electrical characteristics STM32F427xx STM32F429xx Table 108. Dynamic characteristics: SD / MMC characteristics(1)(2) Symbol Parameter Conditions Min fPP Clock frequency in data transfer mode 0 - SDIO_CK/fPCLK2 frequency ratio - tW(CKL) Clock low time fpp =48 MHz tW(CKH) Clock high time fpp =48 MHz Typ Max Unit 48 MHz - 8/3 - 8.5 9 - 8.3 10 - ns CMD, D inputs (referenced to CK) in MMC and SD HS mode tISU Input setup time HS fpp =48 MHz 3.
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Package information 7 STM32F427xx STM32F429xx Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 LQFP100 package information Figure 80. LQFP100 -100-pin, 14 x 14 mm low-profile quad flat package outline MM C ! ! ! 3%!4).' 0,!.
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STM32F427xx STM32F429xx Package information Table 110. LQPF100 100-pin, 14 x 14 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.
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Package information STM32F427xx STM32F429xx Figure 81. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint AI C 1. Dimensions are expressed in millimeters. 200/239 Downloaded from Arrow.com.
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STM32F427xx STM32F429xx Package information Device marking for LQFP100 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which depend on assembly location, are not indicated below. Figure 82. LQFP100 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ 45. ' 5HYLVLRQ FRGH 7*5 3 'DWH FRGH \HDU ZHHN :88 3LQ LGHQWLILHU 67 ORJR DL G 1.
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Package information 7.2 STM32F427xx STM32F429xx WLCSP143 package information Figure 83. WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package outline $ EDOO ORFDWLRQ H EEE ) * 'HWDLO $ H H H $ $ $ %RWWRP YLHZ %XPS VLGH 6LGH YLHZ ' %XPS $ HHH $ ( E FFF GGG $ RULHQWDWLRQ UHIHUHQFH 7RS YLHZ :DIHU EDFN VLGH = ;< = 6HDWLQJ SODQH 'HWDLO $ 5RWDWHG DDD $ :(B0(B9 1. Drawing is not to scale. 202/239 Downloaded from Arrow.com.
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STM32F427xx STM32F429xx Package information Table 111. WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 0.155 0.175 0.195 - 0.0069 - A2 - 0.380 - - 0.0150 - - 0.025 - - 0.0010 - b(3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 4.486 4.521 4.556 0.1766 0.1780 0.1794 E 5.512 5.547 5.582 0.2170 0.2184 0.
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Package information STM32F427xx STM32F429xx Table 112. WLCSP143 recommended PCB design rules (0.4 mm pitch) Dimension Recommended values Pitch 0.4 260 µm max. (circular) Dpad 220 µm recommended Dsm 300 µm min. (for 260 µm diameter pad) PCB pad design Non-solder mask defined via underbump allowed. Device marking for WLCSP143 The following figure gives an example of topside marking orientation versus ball A 1 identifier location.
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STM32F427xx STM32F429xx 7.3 Package information LQFP144 package information Figure 86. LQFP144-144-pin, 20 x 20 mm low-profile quad flat package outline 6($7,1* 3/$1( F $ $ $ & PP *$8*( 3/$1( ' / ' . $ FFF & / ' ( 3,1 ( ( E ,'(17,),&$7,21 H $B0(B9 1. Drawing is not to scale. DocID024030 Rev 10 205/239 232 Downloaded from Arrow.com.
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Package information STM32F427xx STM32F429xx Table 113. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.874 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.
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STM32F427xx STM32F429xx Package information Figure 87. LQPF144- 144-pin,20 x 20 mm low-profile quad flat package recommended footprint DL H 1. Dimensions are expressed in millimeters. DocID024030 Rev 10 207/239 232 Downloaded from Arrow.com.
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Package information STM32F427xx STM32F429xx Device marking for LQFP144 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which depend on assembly location, are not indicated below. Figure 88. LQFP144 marking example (package top view) 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ 5 ) =(7 'DWH FRGH
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STM32F427xx STM32F429xx 7.4 Package information LQFP176 package information Figure 89. LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package outline C ! ! ! # 3EATING PLANE MM GAUGE PLANE K ! , ($ 0). )$%.4)&)#!4)/. , $ :% % (% E :$ B 4?-%?6 1. Drawing is not to scale. Table 114. LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.
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Package information STM32F427xx STM32F429xx Table 114. LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max ZD - 1.250 - - 0.0492 - E 23.900 - 24.100 0.9409 - 0.9488 HE 25.900 - 26.100 1.0197 - 1.0276 ZE - 1.250 - - 0.0492 - e - 0.500 - - 0.0197 - 0.450 - 0.750 0.0177 - 0.0295 L1 - 1.000 - - 0.0394 - k 0° - 7° 0° - 7° ccc - - 0.080 - - 0.
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STM32F427xx STM32F429xx Package information Figure 90. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat recommended footprint 4?&0?6 1. Dimensions are expressed in millimeters. DocID024030 Rev 10 211/239 232 Downloaded from Arrow.com.
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Package information STM32F427xx STM32F429xx Device marking for LQFP176 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which depend on assembly location, are not indicated below. Figure 91. LQFP176 marking (package top view) 3URGXFW LGHQWLILFDWLRQ 670 ) ,,7 5HYLVLRQ FRGH <:: 'DWH FRGH
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STM32F427xx STM32F429xx 7.5 Package information LQFP208 package information Figure 92. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package outline 6($7,1* 3/$1( F $ $ $ & FFF & PP $ *$8*( 3/$1( . / ' / ' ' 3,1 ,'(17,),&$7,21 ( ( ( E H 6)@.&@7 1. Drawing is not to scale. DocID024030 Rev 10 213/239 232 Downloaded from Arrow.com.
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Package information STM32F427xx STM32F429xx Table 115. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 -- - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 29.800 30.000 30.200 1.1732 1.1811 1.1890 D1 27.800 28.000 28.200 1.0945 1.1024 1.
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STM32F427xx STM32F429xx Package information Figure 93. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package recommended footprint 8+B)3B9 1. Dimensions are expressed in millimeters. DocID024030 Rev 10 215/239 232 Downloaded from Arrow.com.
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Package information STM32F427xx STM32F429xx Device marking for LQFP208 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which depend on assembly location, are not indicated below. Figure 94. LQFP208 marking example (package top view) 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ 5 670 ) %,7 3LQ LGHQWLILHU 'DWH FRGH \HDU ZHHN <:: 06 9 1.
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STM32F427xx STM32F429xx 7.6 Package information UFBGA169 package information Figure 95. UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package outline = 6HDWLQJ SODQH $ $ GGG = $ $ $ E 6,'( 9,(: $ EDOO LGHQWLILHU $ EDOO LQGH[ DUHD ; ( ( H ) $ ) ' ' H < 1 %27720 9,(: 723 9,(: E EDOOV HHH 0 = ; < III 0 = $ <9B0(B9 1. Drawing is not to scale. Table 116. UFBGA169 - 169-ball 7 x 7 mm 0.
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Package information STM32F427xx STM32F429xx Table 116. UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max F 0.450 0.500 0.550 0.0177 0.0197 0.0217 ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 96. UFBGA169 - 169-ball, 7 x 7 mm, 0.
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STM32F427xx STM32F429xx Package information Device marking for UFBGA169 The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which depend on assembly location, are not indicated below. Figure 97. UFBGA169 marking example (package top view) %DOO $ LGHQWLILHU 670 ) 3URGXFW LGHQWLILFDWLRQ $,+ 'DWH FRGH
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Package information 7.7 STM32F427xx STM32F429xx UFBGA176+25 package information Figure 98. UFBGA176+25 - ball 10 x 10 mm, 0.65 mm pitch ultra thin fine pitch ball grid array package outline & ^ĞĂƚŝŶŐ ƉůĂŶĞ ϰ ĚĚĚ ϯ $ ϭ ď Ğ $ EDOO LGHQWLILHU ( $ EDOO LQGH[ DUHD $ ' Ğ Z ϭϱ ϭ KddKD s/ t E EDOOV dKW s/ t HHH 0 & $ III 0 & $ ( B0(B9 1. Drawing is not to scale. Table 118. UFBGA176+25 - ball, 10 x 10 mm, 0.
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STM32F427xx STM32F429xx Package information Table 118. UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 99. UFBGA176+25-ball, 10 x 10 mm, 0.
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Package information STM32F427xx STM32F429xx Device marking for UFBGA176+25 The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which depend on assembly location, are not indicated below. Figure 100. UFBGA176+25 marking example (package top view) 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ 5 670 ) ,,+ 8 'DWH FRGH \HDU ZHHN < :: %DOO LQGHQWLILHU 06 9 1.
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STM32F427xx STM32F429xx 7.8 Package information TFBGA216 package information Figure 101. TFBGA216 - 216 ball 13 × 13 mm 0.8 mm pitch thin fine pitch ball grid array package outline = 6HDWLQJ SODQH GGG = $ $ $ ' H $ EDOO $ EDOO LGHQWLILHU LQGH[ DUHD ) ; ' $ * ( H ( < 5 %27720 9,(: E EDOOV HHH 0 = < ; III 0 = 723 9,(: $ / B0(B9 1. Drawing is not to scale. Table 120. TFBGA216 - 216 ball 13 × 13 mm 0.
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Package information STM32F427xx STM32F429xx Table 120. TFBGA216 - 216 ball 13 × 13 mm 0.8 mm pitch thin fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Device marking for TFBGA176 The following figure gives an example of topside marking orientation versus ball A1 identifier location.
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STM32F427xx STM32F429xx 7.9 Package information Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: • TA max is the maximum ambient temperature in ° C, • ΘJA is the package junction-to-ambient thermal resistance, in ° C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts.
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Part numbering 8 STM32F427xx STM32F429xx Part numbering Table 122.
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STM32F427xx STM32F429xx Appendix A Recommendations when using internal reset OFF Recommendations when using internal reset OFF When the internal reset is OFF, the following integrated features are no longer supported: A.1 • The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled. • The brownout reset (BOR) circuitry must be disabled. • The embedded programmable voltage detector (PVD) is disabled.
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Application block diagrams Appendix B B.1 STM32F427xx STM32F429xx Application block diagrams USB OTG full speed (FS) interface solutions Figure 103. USB controller configured as peripheral-only and used in Full speed mode 6$$ 6 TO 6$$ 6OLATGE REGULATOR 6"53 $- /3#?). 0! 0" $0 0! 0" 633 /3#?/54 53" 3TD " CONNECTOR 34- & XX -3 6 1. External voltage regulator only needed when building a VBUS powered device. 2.
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STM32F427xx STM32F429xx Application block diagrams Figure 105. USB controller configured in dual mode and used in full speed mode 6$$ 6 TO 6$$ VOLTAGE REGULATOR 6$$ '0)/ )21 /VERCURRENT #URRENT LIMITER POWER SWITCH 6 0WR 34- & XX 0! 0" 0! 0" /3#?). /3#?/54 0! 0" 0! 0" 6"53 $$0 )$ 633 53"MICRO !" CONNECTOR '0)/ %. -3 6 1. External voltage regulator only needed when building a VBUS powered device. 2.
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Application block diagrams B.2 STM32F427xx STM32F429xx USB OTG high speed (HS) interface solutions Figure 106. USB controller configured as peripheral, host, or dual-mode and used in high speed mode 34- & XX &3 0(9 53" (3 /4' #TRL $0 $- NOT CONNECTED $0 5,0)?#,+ $- 5,0)?$; = 5,0) )$ 5,0)?$)2 6"53 5,0)?340 53" CONNECTOR 633 5,0)?.84 (IGH SPEED /4' 0(9 0,, 84 OR -(Z 84 -#/ OR -#/ 8) -3 6 1. It is possible to use MCO1 or MCO2 to save a crystal.
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STM32F427xx STM32F429xx B.3 Application block diagrams Ethernet interface solutions Figure 107. MII mode using a 25 MHz crystal 34- -#5 -))?48?#,+ -))?48?%. -))?48$; = -))?#23 -))?#/, %THERNET -!# (#,+ )%%% 040 4IMER INPUT TRIGGER 4IMESTAMP 4)- COMPARATOR %THERNET 0(9 -)) PINS -))?28?#,+ -))?28$; = -))?28?$6 -))?28?%2 -)) -$# PINS -$)/ -$# 003?/54 84!, -(Z /3# 0,, (#,+ -#/ -#/ 0(9?#,+ -(Z 84 -3 6 1. fHCLK must be greater than 25 MHz. 2.
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Application block diagrams STM32F427xx STM32F429xx Figure 109. RMII with a 25 MHz crystal and PHY with PLL 34- & -#5 %THERNET 0(9 2-))?48?%. %THERNET -!# 2-))?48$; = 2-))?28$; = (#,+ )%%% 040 2-))?#28?$6 2-))?2%&?#,+ 2-)) PINS 2%&?#,+ -$)/ 4IMER INPUT TRIGGER 4IMESTAMP 4)- COMPARATOR 2-)) -$# PINS -$# OR OR -(Z SYNCHRONOUS -(Z 84!, -(Z /3# 0,, (#,+ 0,, -#/ -#/ 0(9?#,+ -(Z 84 -3 6 1. fHCLK must be greater than 25 MHz. 2.
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STM32F427xx STM32F429xx 9 Revision history Revision history Table 124. Document revision history Date Revision 19-Mar-2013 1 Initial release. 2 Added STM32F429xx part numbers and related informations. STM32F427xx part numbers: Replaced FSMC by FMC added Chrom-ART Accelerator and SAI interface. Increased core, timer, GPIOs, SPI maximum frequencies Updated Figure 8.Updated Figure 9. Removed note in Section ·: Standby mode. Updated Figure 18.
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Revision history STM32F427xx STM32F429xx Table 124. Document revision history Date 24-Jan-2014 234/239 Downloaded from Arrow.com. Revision Changes 3 Added STM32F429xE part numbers featuring 512 Mbytes of Flash memory and UFBGA169 package. Added LPSDR SDRAM. Changed INTN into INTR in Figure 4: STM32F427xx and STM32F429xx block diagram. Added note 4 in Table 2: STM32F427xx and STM32F429xx features and peripheral counts. Updated Section 3.15: Boot modes.
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STM32F427xx STM32F429xx Revision history Table 124. Document revision history Date 24-Apr-2014 Revision Changes 4 In the whole document, minimum supply voltage changed to 1.7 V when external power supply supervisor is used. Added DCMI_VSYNC alternate function on PG9 and updated note 6. in Table 10: STM32F427xx and STM32F429xx pin and ball definitions and Table 12: STM32F427xx and STM32F429xx alternate function mapping. Added note 2.belowFigure 16: STM32F42x UFBGA169 ballout.
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Revision history STM32F427xx STM32F429xx Table 124. Document revision history Date Revision Changes Update SPI/IS2 in Table 2: STM32F427xx and STM32F429xx features and peripheral counts. Updated LQFP208 in Table 4: Regulator ON/OFF and internal reset ON/OFF availability. Updated Figure 19: Memory map. Changed PLS[2:0]=101 (falling edge) maximum value in Table 22: reset and power control block characteristics. 19-Feb-2015 236/239 Downloaded from Arrow.com.
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STM32F427xx STM32F429xx Revision history Table 124. Document revision history Date Revision Changes 6 Updated notes related to the minimum and maximum values guaranteed by design, characterization or test in production. Updated IDD_STOP_UDM in Table 27: Typical and maximum current consumptions in Stop mode.
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Revision history STM32F427xx STM32F429xx Table 124. Document revision history Date Revision Changes Updated Figure 1: Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package. Added mission profile compliance with JEDEC JESD47 in Section 6.2: Absolute maximum ratings. 18-Jul-2016 9 Changed Figure 31 HSI deviation versus temperature to ACCHSI versus temperature. Updated RLOAD in Table 85: DAC characteristics. Added note 2. related to the position of the 0.
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STM32F427xx STM32F429xx IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.