Datasheet

Electrical characteristics STM32F427xx STM32F429xx
144/239 DocID024030 Rev 10
t
w(SCKH)
SCK high and low time
Master mode, SPI presc = 2,
2.7 V≤V
DD
≤3.6 V
T
PCLK
− 0.5
T
PCLK
T
PCLK
+0.5
ns
t
w(SCKL)
Master mode, SPI presc = 2,
1.7 V≤V
DD
≤3.6 V
T
PCLK
− 2
T
PCLK
T
PCLK
+2
t
su(NSS)
NSS setup time Slave mode, SPI presc = 2 4T
PCLK
--
t
h(NSS)
NSS hold time Slave mode, SPI presc = 2 2T
PCLK
t
su(MI)
Data input setup time
Master mode 3 - -
t
su(SI)
Slave mode 0 - -
t
h(MI)
Data input hold time
Master mode 0.5 - -
t
h(SI)
Slave mode 2 - -
t
a(SO
) Data output access time Slave mode, SPI presc = 2 0 - 4T
PCLK
t
dis(SO)
Data output disable time
Slave mode, SPI1/4/5/6,
2.7 V≤V
DD
≤3.6 V
0-8.5
Slave mode, SPI1/2/3/4/5/6 and
1.7 V≤V
DD
≤3.6 V
0-16.5
t
v(SO)
t
h(SO)
Data output valid/hold
time
Slave mode (after enable edge),
SPI1/4/5/6 and 2.7V ≤ V
DD
≤ 3.6V
-1113
ns
Slave mode (after enable edge),
SPI2/3, 2.7 V≤V
DD
≤3.6 V
-1415
Slave mode (after enable edge),
SPI1/4/5/6, 1.7 V≤V
DD
≤3.6 V
-15.519
Slave mode (after enable edge),
SPI2/3, 1.7 V≤V
DD
≤3.6 V
- 15.5 17.5
t
v(MO)
Data output valid time
Master mode (after enable edge),
SPI1/4/5/6, 2.7 V≤V
DD
≤3.6 V
--2.5
Master mode (after enable edge),
SPI1/2/3/4/5/6, 1.7 V≤V
DD
≤3.6 V
--4.5
t
h(MO)
Data output hold time
Master mode (after enable edge) 0 - -
1. Guaranteed by characterization results.
2. Maximum frequency in Slave transmitter mode is determined by the sum of t
v(SO)
and t
su(MI)
which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having t
su(MI)
= 0 while Duty(SCK) = 50%
Table 62. SPI dynamic characteristics
(1)
(continued)
Symbol Parameter Conditions Min Typ Max Unit
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