Datasheet

Electrical characteristics STM32F427xx STM32F429xx
138/239 DocID024030 Rev 10
Output voltage levels
Unless otherwise specified, the parameters given in Table 57 are derived from tests
performed under ambient temperature and V
DD
supply voltage conditions summarized in
Table 17 . All I/Os are CMOS and TTL compliant.
Table 57. Output voltage characteristics
Symbol Parameter Conditions Min Max Unit
V
OL
(1)
1. The I
IO
current sunk by the device must always respect the absolute maximum rating specified in Table 15.
and the sum of I
IO
(I/O ports and control pins) must not exceed I
VSS
.
Output low level voltage for an I/O pin CMOS port
(2)
I
IO
= +8 mA
2.7 V
≤ V
DD
≤ 3.6 V
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
-0.4
V
V
OH
(3)
3. The I
IO
current sourced by the device must always respect the absolute maximum rating specified in
Table 15 and the sum of I
IO
(I/O ports and control pins) must not exceed I
VDD
.
Output high level voltage for an I/O pin V
DD
− 0.4 -
V
OL
(1)
Output low level voltage for an I/O pin TTL port
(2)
I
IO
=+ 8mA
2.7 V
≤ V
DD
≤ 3.6 V
-0.4
V
V
OH
(3)
Output high level voltage for an I/O pin 2.4 -
V
OL
(1)
Output low level voltage for an I/O pin
I
IO
= +20 mA
2.7 V
≤ V
DD
≤ 3.6 V
-1.3
(4)
4. Based on characterization data.
V
V
OH
(3)
Output high level voltage for an I/O pin V
DD
−1.3
(4)
-
V
OL
(1)
Output low level voltage for an I/O pin
I
IO
= +6 mA
1.8 V
≤ V
DD
≤ 3.6 V
-0.4
(4)
V
V
OH
(3)
Output high level voltage for an I/O pin V
DD
−0.4
(4)
-
V
OL
(1)
Output low level voltage for an I/O pin
I
IO
= +4 mA
1.7 V
≤ V
DD
≤ 3.6V
-0.4
(5)
5. Guaranteed by design.
V
V
OH
(3)
Output high level voltage for an I/O pin V
DD
−0.4
(5)
-
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