Datasheet

Electrical characteristics STM32F427xx STM32F429xx
126/239 DocID024030 Rev 10
I
DD(PLLI2S)
(4)
PLLI2S power consumption on
V
DD
VCO freq = 100 MHz
VCO freq = 432 MHz
0.15
0.45
-
0.40
0.75
mA
I
DDA(PLLI2S)
(4)
PLLI2S power consumption on
V
DDA
VCO freq = 100 MHz
VCO freq = 432 MHz
0.30
0.55
-
0.40
0.85
mA
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Guaranteed by characterization results.
Table 44. PLLI2S (audio PLL) characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 45. PLLISAI (audio and LCD-TFT PLL) characteristics
Symbol Parameter Conditions Min Typ Max Unit
f
PLLSAI_IN
PLLSAI input clock
(1)
0.95
(2)
12.10MHz
f
PLLSAI_OUT
PLLSAI multiplier output clock - - 216 MHz
f
VCO_OUT
PLLSAI VCO output 100 - 432 MHz
t
LOCK
PLLSAI lock time
VCO freq = 100 MHz 75 - 200
µs
VCO freq = 432 MHz 100 - 300
Jitter
(3)
Main SAI clock jitter
Cycle to cycle at
12.288 MHz on
48KHz period,
N=432, R=5
RMS - 90 -
peak
to
peak
- ±280 - ps
Average frequency of
12.288 MHz
N = 432, R = 5
on 1000 samples
-90 -ps
FS clock jitter
Cycle to cycle at 48 KHz
on 1000 samples
-400 - ps
I
DD(PLLSAI)
(4)
PLLSAI power consumption on
V
DD
VCO freq = 100 MHz
VCO freq = 432 MHz
0.15
0.45
-
0.40
0.75
mA
I
DDA(PLLSAI)
(4)
PLLSAI power consumption on
V
DDA
VCO freq = 100 MHz
VCO freq = 432 MHz
0.30
0.55
-
0.40
0.85
mA
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Guaranteed by characterization results.
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