Datasheet

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STM32F427xx STM32F429xx Electrical characteristics
198
Figure 62. Synchronous non-multiplexed PSRAM write timings
t
h(CLKH-DV)
FMC_D[15:0] valid data after FMC_CLK high 0 - ns
t
(NWAIT-CLKH)
FMC_NWAIT valid before FMC_CLK high 4
t
h(CLKH-
NWAIT)
FMC_NWAIT valid after FMC_CLK high 0
1. C
L
= 30 pF.
2. Guaranteed by characterization results.
Table 97. Synchronous non-multiplexed PSRAM write timings
(1)(2)
Symbol Parameter Min Max Unit
t
(CLK)
FMC_CLK period 2T
HCLK
− 1 - ns
t
d(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2) - 0.5 ns
t
(CLKH-NExH)
FMC_CLK high to FMC_NEx high (x= 0…2) T
HCLK
-ns
t
d(CLKL-NADVL)
FMC_CLK low to FMC_NADV low - 0 ns
t
d(CLKL-NADVH)
FMC_CLK low to FMC_NADV high 0 - ns
t
d(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x=16…25) - 0 ns
Table 96. Synchronous non-multiplexed NOR/PSRAM read timings
(1)(2)
(continued)
Symbol Parameter Min Max Unit
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