Datasheet

DocID024030 Rev 10 179/239
STM32F427xx STM32F429xx Electrical characteristics
198
Table 95. Synchronous multiplexed PSRAM write timings
(1)(2)
1. C
L
= 30 pF.
2. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
t
w(CLK)
FMC_CLK period, VDD range= 2.7 to 3.6 V 2T
HCLK
− 1 - ns
t
d(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2) - 1.5 ns
t
d(CLKH-NExH)
FMC_CLK high to FMC_NEx high (x= 0…2) T
HCLK
-ns
t
d(CLKL-NADVL)
FMC_CLK low to FMC_NADV low - 0 ns
t
d(CLKL-NADVH)
FMC_CLK low to FMC_NADV high 0 - ns
t
d(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x=16…25) - 0 ns
t
d(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid (x=16…25) T
HCLK
-ns
t
d(CLKL-NWEL)
FMC_CLK low to FMC_NWE low - 0 ns
t
(CLKH-NWEH)
FMC_CLK high to FMC_NWE high T
HCLK
−0.5 - ns
t
d(CLKL-ADV)
FMC_CLK low to FMC_AD[15:0] valid - 3 ns
t
d(CLKL-ADIV)
FMC_CLK low to FMC_AD[15:0] invalid 0 - ns
t
d(CLKL-DATA)
FMC_A/D[15:0] valid data after FMC_CLK low - 3 ns
t
d(CLKL-NBLL)
FMC_CLK low to FMC_NBL low 0 - ns
t
d(CLKH-NBLH)
FMC_CLK high to FMC_NBL high T
HCLK
−0.5 - ns
t
su(NWAIT-CLKH)
FMC_NWAIT valid before FMC_CLK high 4 - ns
t
h(CLKH-NWAIT)
FMC_NWAIT valid after FMC_CLK high 0 - ns
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