Datasheet

Electrical characteristics STM32F427xx STM32F429xx
142/239 DocID024030 Rev 10
6.3.19 TIM timer characteristics
The parameters given in Table 60 are guaranteed by design.
Refer to Section 6.3.17: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
6.3.20 Communications interfaces
I
2
C interface characteristics
The I
2
C interface meets the timings requirements of the I
2
C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s.
The I
2
C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0090 reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and V
DD
is disabled, but is still present. Refer to
Section 6.3.17: I/O port characteristics
for more details on the I
2
C I/O characteristics
.
All I
2
C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
Table 60. TIMx characteristics
(1)(2)
1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers.
2. Guaranteed by design.
Symbol Parameter
Conditions
(3)
3. The maximum timer frequency on APB1 or APB2 is up to 180 MHz, by setting the TIMPRE bit in the
RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise TIMxCLK =
4x PCLKx.
Min Max Unit
t
res(TIM)
Timer resolution time
AHB/APBx prescaler=1
or 2 or 4, f
TIMxCLK
=
180 MHz
1-
t
TIMxCLK
AHB/APBx prescaler>4,
f
TIMxCLK
= 90 MHz
1-
t
TIMxCLK
f
EXT
Timer external clock
frequency on CH1 to CH4
f
TIMxCLK
= 180 MHz
0
f
TIMxCLK
/2
MHz
Res
TIM
Timer resolution - 16/32 bit
t
MAX_COUNT
Maximum possible count
with 32-bit counter
-
65536 ×
65536
t
TIMxCLK
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