Datasheet
DocID022063 Rev 8 41/206
STM32F415xx, STM32F417xx Description
2.2.33 Cryptographic acceleration
The STM32F415xx and STM32F417xx devices embed a cryptographic accelerator. This
cryptographic accelerator provides a set of hardware acceleration for the advanced
cryptographic algorithms usually needed to provide confidentiality, authentication, data
integrity and non repudiation when exchanging messages with a peer.
These algorithms consists of:
Encryption/Decryption
– DES/TDES (data encryption standard/triple data encryption standard): ECB
(electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-,
128- or 192-bit key
– AES (advanced encryption standard): ECB, CBC and CTR (counter mode)
chaining algorithms, 128, 192 or 256-bit key
Universal hash
– SHA-1 (secure hash algorithm)
–MD5
–HMAC
The cryptographic accelerator supports DMA request generation.
2.2.34 Random number generator (RNG)
All STM32F415xx and STM32F417xx products embed an RNG that delivers 32-bit random
numbers generated by an integrated analog circuit.
2.2.35 General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 84 MHz.
2.2.36 Analog-to-digital converters (ADCs)
Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16
external channels, performing conversions in the single-shot or scan mode. In scan mode,
automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
• Simultaneous sample and hold
• Interleaved sample and hold
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
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