Datasheet

List of figures STM32F415xx, STM32F417xx
10/206 DocID022063 Rev 8
List of figures
Figure 1. Compatible board design between STM32F10xx/STM32F41xxx for LQFP64 . . . . . . . . . . 17
Figure 2. Compatible board design STM32F10xx/STM32F2/STM32F41xxx
for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 3. Compatible board design between STM32F10xx/STM32F2/STM32F41xxx
for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 4. Compatible board design between STM32F2 and STM32F41xxx
for LQFP176 and BGA176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 5. STM32F41xxx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 6. Multi-AHB matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 7. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 27
Figure 8. PDR_ON and NRST control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 9. Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 10. Startup in regulator OFF mode: slow V
DD
slope
- power-down reset risen after V
CAP_1
/V
CAP_2
stabilization . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 11. Startup in regulator OFF mode: fast V
DD
slope
- power-down reset risen before V
CAP_1
/V
CAP_2
stabilization . . . . . . . . . . . . . . . . . . . . . . 31
Figure 12. STM32F41xxx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 13. STM32F41xxx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 14. STM32F41xxx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 15. STM32F41xxx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 16. STM32F41xxx UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 17. STM32F41xxx WLCSP90 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 18. STM32F41xxx memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 19. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 20. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 21. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 22. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 23. External capacitor C
EXT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 24. Typical current consumption versus temperature, Run mode, code with data
processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF . . . . 90
Figure 25. Typical current consumption versus temperature, Run mode, code with data
processing running from Flash (ART accelerator ON) or RAM, and peripherals ON . . . . . 90
Figure 26. Typical current consumption versus temperature, Run mode, code with data
processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF . . . 91
Figure 27. Typical current consumption versus temperature, Run mode, code with data
processing running from Flash (ART accelerator OFF) or RAM, and peripherals ON . . . . 91
Figure 28. Typical V
BAT
current consumption (LSE and RTC ON/backup RAM OFF) . . . . . . . . . . . . 94
Figure 29. Typical V
BAT
current consumption (LSE and RTC ON/backup RAM ON) . . . . . . . . . . . . . 95
Figure 30. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 31. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 32. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 33. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 34. ACC
LSI
versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 35. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 36. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 37. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 38. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 39. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
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