Datasheet

DocID029162 Rev 6 39/208
STM32F413xG/H Functional overview
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Different sources can also be selected for the SAI. The different possible sources are the
main PLL, the PLLI2S, HSE or HSI clocks or an external clock provided through a pin
(external PLL or CODEC output).
The PLLI2S configuration can be modified to manage an I
2
S/SAI sample rate change
without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8
KHz to 192 KHz.
3.29 Digital filter for sigma-delta modulators (DFSDM)
The device embeds two DFSDMs:
• DFSDM1 has 2 digital filters modules and 4 external input serial channels
(transceivers) or alternately 2 internal parallel inputs support.
• DFSDM2 features 4 digital filters modules and 8 external input serial channels
(transceivers) or alternately 4 internal parallel inputs support.
The amount of filters defines the number of conversions which can be performed
simultaneously.
The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse
Density Modulation) microphones and perform PDM to PCM conversion and filtering in
hardware. It is also possible to introduce a programmable delay between different
microphones (beamforming feature). DFSDM features optional parallel data stream inputs
from microcontrollers memory (through DMA/CPU transfers into DFSDM).
DFSDM transceivers support several serial interface formats (to support various Σ∆
modulators). DFSDM digital filter modules perform digital processing according user
selected filter parameters with up to 24-bit final ADC resolution.
3.30 Dynamic tuning of PDM delays for sound source localization
A mechanism is implemented on top of the DFSDM allowing to dynamically tune PDM
delays of each microphone without the need to add external delay lines.
Audio application with several microphones require strong microphones placement
constraints, as the distance between the microphones must be a multiple of v/F where v is
the speed of the sound and F is the PCM sampling frequency.
The designed mechanism removes this constraint by programming delays for each digital
microphone with the granularity of the PDM clock rate prior to the conversion into PCM rate.
The tuning delay is performed by a clock skipping technique.
Table 8. DFSDM feature comparison
DFSDM instance
External input serial
channels
External input parallel
channels
Digital filters
DFSDM1 4 2 2
DFSDM2 8 4 4
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