Datasheet

DocID029162 Rev 6 21/208
STM32F413xG/H Functional overview
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3.7 Embedded SRAM
All devices embed 320 Kbytes of system SRAM which can be accessed (read/write) at CPU
clock speed with 0 wait states.
3.8 Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves
(Flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient
operation even when several high-speed peripherals work simultaneously.
Figure 5. Multi-AHB matrix
CPU can access SRAM1 memory via S-bus, when SRAM1 is mapped at the address range:
0x2000 0000 to 0x2003 FFFF.
CPU can access SRAM2 memory via S-bus, when SRAM2 is mapped at the address range:
0x2004 0000 to 0x2004 FFFF.
CPU can access SRAM1 memory via I-bus and D-bus, when SRAM1 is remapped at
address 0x0000 0000 either by booting from RAM memory or by the remap mode.
CPU can access SRAM2 memory via I-bus and D-bus, when SRAM2 is mapped at the
address range: 0x1000 0000 to 0x1000 FFFF.
Performance boosts up, when the CPU access SRAM memory via the I-bus.
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