Datasheet

DocID029162 Rev 6 139/208
STM32F413xG/H Electrical characteristics
174
SAI characteristics
Unless otherwise specified, the parameters given in Tabl e 69 for SAI are derived from tests
performed under the ambient temperature, f
PCLKx
frequency and VDD supply voltage
conditions summarized in
Table 17, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C=30 pF
• Measurement points are performed at CMOS levels: 0.5V
DD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (SCK,SD,WS).
Table 69. SAI characteristics
(1)
Symbol Parameter Conditions Min Max Unit
f
MCKL
SAI Main clock output - 256 * 8K 256 * Fs
(2)
MHz
F
SCK
SAI clock frequency
Master data: 32 bits - 128 * Fs
MHz
Slave data: 32 bits - 128 * Fs
t
v(FS)
FS valid time
Master mode
2.7 V <= V
DD
<= 3.6 V
-19
ns
Master mode
1.71 V <= V
DD
<= 3.6 V
-28
t
h(FS)
FS hold time
Master mode 13 -
Slave mode 0 -
t
su(FS)
FS setup time Slave mode 3 -
t
su(SD_ A_MR)
Data input setup time
Master receiver 0.5 -
t
su(SD_B_SR)
Slave receiver 1.5 -
t
h(SD_ A_MR)
Data input hold time
Master receiver 5 -
t
h(SD_B_SR)
Slave receiver 2.5 -
t
v(SD_B_ST)
Data output valid time
Slave transmitter (after enable edge)
2.7 V <= V
DD
<= 3.6 V
-15
Slave transmitter (after enable edge)
1.71 V <= V
DD
<= 3.6 V
-28
t
h(SD_B_ST)
Data output hold time Slave transmitter (after enable edge) 10 -
t
v(SD_A_MT)
Data output valid time
Master transmitter (after enable edge)
2.7 V <= V
DD
<= 3.6 V
-15
Master transmitter (after enable edge)
1.71 V <= V
DD
<= 3.6 V
-29
t
h(SD_A_MT)
Data output hold time Master transmitter (after enable edge) 13 -
1. Guaranteed by characterization results.
2. 256 * Fs maximum corresponds to 45 MHz (APB2 maximum frequency)
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