Datasheet

Functional overview STM32F413xG/H
24/208 DocID029162 Rev 6
buses and high-speed APB domains is 100 MHz. The maximum allowed frequency of the
low-speed APB domain is 50
MHz.
The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class
performance. In this case, the I
2
S master clock can generate all standard sampling
frequencies from 8
kHz to 192 kHz.
3.15 Boot modes
At startup, boot pins are used to select one out of three boot options:
• Boot from user Flash memory
• Boot from system memory
• Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using one of the interface listed in the
Table 3 or the USB OTG FS in device mode through
DFU (device firmware upgrade).
For more detailed information on the bootloader, refer to Application Note: AN2606,
STM32™ microcontroller system memory boot mode.
Table 3. Embedded bootloader interfaces
Package
USART1
PA9/
PA10
USART2
PD6/
PD5
USART3
PB11/
PB10
I2C1
PB6/
PB7
I2C2
PF0/
PF1
I2C3
PA8/
PB4
I2C
FMP1
PB14/
PB15
SPI1
PA4/
PA5/
PA6/
PA7
SPI3
PA15/
PC10/
PC11/
PC12
SPI4
PE11/
PE12/
PE13/
PE14
CAN2
PB5/
PB13
USB
PA11
/P12
UFQFPN48 Y - - Y - Y Y Y - - Y Y
LQFP64 Y - - Y - Y Y Y Y - Y Y
WLCSP81 Y - - Y - Y Y Y Y Y Y Y
LQFP100Y Y - Y-YYYYYYY
LQFP144YYYYYYYYYYYY
UFBGA100 Y Y Y Y - Y Y Y Y Y Y Y
UFBGA144 Y Y Y Y Y Y Y Y Y Y Y Y
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