Datasheet

DocID029162 Rev 6 163/208
STM32F413xG/H Electrical characteristics
174
Table 92. Asynchronous multiplexed PSRAM/NOR read timings
(1)(2)
1. C
L
= 30 pF.
2. Based on characterization.
Symbol Parameter Min Max Unit
t
w(NE)
FSMC_NE low time 3 * t
HCLK
- 1 3 * t
HCLK
+ 1
ns
t
v(NOE_NE)
FSMC_NEx low to FSMC_NOE low 2 * t
HCLK
2 * t
HCLK
+ 0.5
t
w(NOE)
FSMC_NOE low time t
HCLK
- 1 t
HCLK
+ 1
t
h(NE_NOE)
FSMC_NOE high to FSMC_NE high hold
time
0-
t
v(A_NE)
FSMC_NEx low to FSMC_A valid - 0.5
t
v(NADV_NE)
FSMC_NEx low to FSMC_NADV low 0 0.5
t
w(NADV)
FSMC_NADV low time t
HCLK
- 0.5 t
HCLK
+ 1
t
h(AD_NADV)
FSMC_AD(address) valid hold time after
FSMC_NADV high)
t
HCLK
+ 0.5 -
t
h(A_NOE)
Address hold time after FSMC_NOE high t
HCLK
- 0.5 -
t
h(BL_NOE)
FSMC_BL time after FSMC_NOE high 0 -
t
v(BL_NE)
FSMC_NEx low to FSMC_BL valid - 0.5
t
su(Data_NE)
Data to FSMC_NEx high setup time t
HCLK
- 2 -
t
su(Data_NOE)
Data to FSMC_NOE high setup time t
HCLK
- 2 -
t
h(Data_NE)
Data hold time after FSMC_NEx high 0 -
t
h(Data_NOE)
Data hold time after FSMC_NOE high 0 -
Table 93. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings
(1)(2)
1. C
L
= 30 pF.
2. Based on characterization.
Symbol Parameter Min Max Unit
t
w(NE)
FSMC_NE low time 8 * t
HCLK
- 1
8 * t
HCLK
+ 1
ns
t
w(NOE)
FSMC_NWE low time 5 * t
HCLK
- 1.5 5 * t
HCLK
+ 0.5
t
su(NWAIT_NE)
FSMC_NWAIT valid before FSMC_NEx
high
5 * t
HCLK
+ 1.5 -
t
h(NE_NWAIT)
FSMC_NEx hold time after
FSMC_NWAIT invalid
4 * t
HCLK
+ 1 -
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