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STM32F413xG/H Electrical characteristics
174
6.3.25 DFSDM characteristics
Unless otherwise specified, the parameters given in Table 87 for DFSDM are derived from
tests performed under the ambient temperature, f
APB2
frequency and V
DD
supply voltage
conditions summarized in
Table 17: General operating conditions.
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 * V
DD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (DFSDM_CKINy, DFSDM_DATINy, DFSDM_CKOUT for DFSDM).
Table 87. DFSDM characteristics
(1)
Symbol Parameter Conditions Min Typ Max Unit
f
DFSDMCLK
DFSDM clock 1.71 < V
DD
< 3.6 V - - f
SYSCLK
MHz
f
CKIN
(1/T
CKIN
)
Input clock
frequency
SPI mode
(SITP[1:0] = 0,1),
External clock mode
(SPICKSEL[1:0] = 0,
1.71 < V
DD
< 3.6 V
--
20
(f
DFBDMCLK
/ 4
SPI mode
(SITP[1:0] = 0,1),
External clock mode
(SPICKSEL[1:0] = 0,
2.7 < V
DD
< 3.6 V
--
20
(f
DFBDMCLK
/ 4
SPI mode
(SITP[1:0] = 0,1),
Internal clock mode
(SPICKSEL[1:0] ≠ 0,
1.71 < V
DD
< 3.6 V
--
20
(f
DFBDMCLK
/ 4
SPI mode (SITP[1:0] = 0,1),
Internal clock mode
(SPICKSEL[1:0] ≠ 0,
2.7 < V
DD
< 3.6 V
--
20
(f
DFBDMCLK
/ 4
f
CKOUT
Output clock
frequency
1.71 < V
DD
< 3.6 V - - 20
DuCy
CKOUT
Output clock
frequency duty
cycle
1.71 < V
DD
< 3.6 V 45 50 55 %
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