Datasheet

DocID029162 Rev 6 153/208
STM32F413xG/H Electrical characteristics
174
DNL
(4)
Differential non
linearity Difference
between two
consecutive code-
1LSB)
- - - ±0.5 LSB
Given for the DAC in 10-bit
configuration.
---±2 LSB
Given for the DAC in 12-bit
configuration.
INL
(4)
Integral non
linearity (difference
between measured
value at Code i and
the value at Code i
on a line drawn
between Code 0
and last Code
1023)
---±1LSB
Given for the DAC in 10-bit
configuration.
---±4LSB
Given for the DAC in 12-bit
configuration.
Offset
(4)
Offset error
(difference between
measured value at
Code (0x800) and
the ideal value =
V
REF+
/2)
---±10mV
Given for the DAC in 12-bit
configuration
---±3LSB
Given for the DAC in 10-bit at
V
REF+
= 3.6 V
---±12LSB
Given for the DAC in 12-bit at
V
REF+
= 3.6 V
Gain
error
(4)
Gain error - - - ±0.5 %
Given for the DAC in 12-bit
configuration
t
SETTLING
(
4)
Settling time (full
scale: for a 10-bit
input code transition
between the lowest
and the highest
input codes when
DAC_OUT reaches
final value ±4LSB
--36µs
C
LOAD
≤ 50 pF,
R
LOAD
≥ 5 kΩ
THD
(4)
Total Harmonic
Distortion
Buffer ON
----dB
C
LOAD
≤ 50 pF,
R
LOAD
≥ 5 kΩ
Update
rate
(2)
Max frequency for a
correct DAC_OUT
change when small
variation in the input
code (from code i to
i+1LSB)
---1MS/s
C
LOAD
≤ 50 pF,
R
LOAD
≥ 5 kΩ
t
WAKEUP
(4)
Wakeup time from
off state (Setting the
ENx bit in the DAC
Control register)
--6.510µs
C
LOAD
≤ 50 pF, R
LOAD
≥ 5 kΩ
input code between lowest and
highest possible ones.
PSRR+
(2)
Power supply
rejection ratio (to
V
DDA
) (static DC
measurement)
- - –67 –40 dB No R
LOAD
, C
LOAD
= 50 pF
Table 86. DAC characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit Comments
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