Datasheet

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STM32F412xE/G Electrical characteristics
161
6.3.26 SD/SDIO MMC/eMMC card host interface (SDIO) characteristics
Unless otherwise specified, the parameters given in Table 95 for the SDIO are derived from
tests performed under the ambient temperature, f
PCLK2
frequency and V
DD
supply voltage
conditions summarized in Table 15, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output
characteristics.
Table 94. Synchronous non-multiplexed PSRAM write timings
(1)(2)
1. C
L
= 30 pF.
2. Based on characterization, not tested in production.
Symbol Parameter Min Max Unit
t
w(CLK)
FSMC_CLK period 2T
HCLK
– 0.5 -
ns
t
d(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x=0..2) - 1
t
d(CLKH-NExH)
FSMC_CLK high to FSMC_NEx high (x= 0…2) T
HCLK
+ 0.5 -
t
d(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low - 1
t
d(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high 0 -
t
d(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x=16…25) - 2
t
d(CLKH-AIV)
FSMC_CLK high to FSMC_Ax invalid (x=16…25) T
HCLK
-
t
d(CLKL-NWEL)
FSMC_CLK low to FSMC_NWE low - 1.5
t
d(CLKH-NWEH)
FSMC_CLK high to FSMC_NWE high T
HCLK
+ 0.5 -
t
d(CLKL-Data)
FSMC_D[15:0] valid data after FSMC_CLK low - 4
t
d(CLKL-NBLL)
FSMC_CLK low to FSMC_NBL low - 3
t
d(CLKH-NBLH)
FSMC_CLK high to FSMC_NBL high T
HCLK
-
t
su(NWAIT-
CLKH)
FSMC_NWAIT valid before FSMC_CLK high 2 -
t
h(CLKH-NWAIT)
FSMC_NWAIT valid after FSMC_CLK high 2 -
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