Datasheet

Electrical characteristics STM32F412xE/G
152/193 DocID028087 Rev 4
Synchronous waveforms and timings
Figure 54 through Figure 57 represent synchronous waveforms and Table 91 through
Table 94 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
• BurstAccessMode = FSMC_BurstAccessMode_Enable;
• MemoryType = FSMC_MemoryType_CRAM;
• WriteBurst = FSMC_WriteBurst_Enable;
• CLKDivision = 1; (0 is not supported, see the STM32F446 reference manual: RM0390)
• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
Table 89. Asynchronous multiplexed PSRAM/NOR write timings
(1)(2)
1. C
L
= 30 pF.
2. Based on characterization, not tested in production.
Symbol Parameter Min Max Unit
t
w(NE)
FSMC_NE low time 4T
HCLK
- 1 4T
HCLK
+0.5
ns
t
v(NWE_NE)
FSMC_NEx low to FSMC_NWE low T
HCLK
T
HCLK
+ 1
t
w(NWE)
FSMC_NWE low time 2T
HCLK
- 1 2T
HCLK
+ 0.5
t
h(NE_NWE)
FSMC_NWE high to FSMC_NE high hold time T
HCLK
- 1.5 -
t
v(A_NE)
FSMC_NEx low to FSMC_A valid - 2
t
v(NADV_NE)
FSMC_NEx low to FSMC_NADV low 0 1
t
w(NADV)
FSMC_NADV low time T
HCLK
– 0.5 T
HCLK
+ 0.5
t
h(AD_NADV)
FSMC_AD(adress) valid hold time after
FSMC_NADV high)
T
HCLK
-
t
h(A_NWE)
Address hold time after FSMC_NWE high T
HCLK
- 1.5 -
t
h(BL_NWE)
FSMC_BL hold time after FSMC_NWE high T
HCLK
-
t
v(BL_NE)
FSMC_NEx low to FSMC_BL valid - 1.5
t
v(Data_NADV)
FSMC_NADV high to Data valid - T
HCLK
+ 2
t
h(Data_NWE)
Data hold time after FSMC_NWE high T
HCLK
+ 0.5 -
Table 90. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings
(1)(2)
1. C
L
= 30 pF.
2. Based on characterization, not tested in production.
Symbol Parameter Min Max Unit
t
w(NE)
FSMC_NE low time 9T
HCLK
- 1 9T
HCLK
+ 0.5
ns
t
w(NWE)
FSMC_NWE low time 7T
HCLK
- 1 7T
HCLK
+ 0.5
t
su(NWAIT_NE)
FSMC_NWAIT valid before FSMC_NEx high 6T
HCLK
-1 -
t
h(NE_NWAIT)
FSMC_NEx hold time after FSMC_NWAIT
invalid
4T
HCLK
+ 1 -
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