Datasheet

Electrical characteristics STM32F412xE/G
150/193 DocID028087 Rev 4
Table 87. Asynchronous multiplexed PSRAM/NOR read timings
(1)(2)
1. C
L
= 30 pF.
2. Based on characterization, not tested in production.
Symbol Parameter Min Max Unit
t
w(NE)
FSMC_NE low time 3T
HCLK
– 1 3T
HCLK
+ 0.5
ns
t
v(NOE_NE)
FSMC_NEx low to FSMC_NOE low 2T
HCLK
2T
HCLK
+ 1
t
tw(NOE)
FSMC_NOE low time T
HCLK
– 1.5 T
HCLK
t
h(NE_NOE)
FSMC_NOE high to FSMC_NE high hold
time
0 -
t
v(A_NE)
FSMC_NEx low to FSMC_A valid - 0.5
t
v(NADV_NE)
FSMC_NEx low to FSMC_NADV low 0 1
t
w(NADV)
FSMC_NADV low time T
HCLK
– 0.5 T
HCLK
+ 0.5
t
h(AD_NADV)
FSMC_AD(address) valid hold time after
FSMC_NADV high)
0 -
t
h(A_NOE)
Address hold time after FSMC_NOE high T
HCLK
– 0.5 -
t
h(BL_NOE)
FSMC_BL time after FSMC_NOE high 0 -
t
v(BL_NE)
FSMC_NEx low to FSMC_BL valid - 0.5
t
su(Data_NE)
Data to FSMC_NEx high setup time T
HCLK
- 2 -
t
su(Data_NOE)
Data to FSMC_NOE high setup time T
HCLK
- 2 -
t
h(Data_NE)
Data hold time after FSMC_NEx high 0 -
t
h(Data_NOE)
Data hold time after FSMC_NOE high 0 -
Table 88. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings
(1)(2)
1. C
L
= 30 pF.
2. Based on characterization, not tested in production.
Symbol Parameter Min Max Unit
t
w(NE)
FSMC_NE low time 8T
HCLK
- 1 8T
HCLK
+ 0.5
ns
t
w(NOE)
FSMC_NWE low time 5T
HCLK
5T
HCLK
+ 0.5
t
su(NWAIT_NE)
FSMC_NWAIT valid before FSMC_NEx
high
5T
HCLK
- 1 -
t
h(NE_NWAIT)
FSMC_NEx hold time after
FSMC_NWAIT invalid
4T
HCLK
+ 1 -
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