Datasheet

Electrical characteristics STM32F412xE/G
144/193 DocID028087 Rev 4
6.3.24 DFSDM characteristics
Unless otherwise specified, the parameters given in Table 8 2 for DFSDM are derived from
tests performed under the ambient temperature, f
APB2
frequency and V
DD
supply voltage
conditions summarized in Table 15: General operating conditions.
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 ₓ VDD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (DFSDM_CKINy, DFSDM_DATINy, DFSDM_CKOUT for DFSDM).
Table 82. DFSDM characteristics
(1)
Symbol Parameter Conditions Min Typ Max Unit
f
DFSDMCLK
DFSDM clock - - - f
SYSCLK
MHz
f
CKIN
(1/T
CKIN
)
Input clock
frequency
SPI mode (SITP[1:0] = 01) - -
20
(f
DFSDMCLK
/4)
f
CKOUT
Output clock
frequency
---20MHz
DuCy
CKOUT
Output clock
frequency
duty cycle
-305075%
t
wh(CKIN)
t
wl(CKIN)
Input clock
high and low
time
SPI mode (SITP[1:0] = 01),
External clock mode
(SPICKSEL[1:0] = 0)
T
CKIN
/2-0.5 T
CKIN
/2 -
ns
t
su
Data input
setup time
SPI mode (SITP[1:0]=01),
External clock mode
(SPICKSEL[1:0] = 0)
1- -
t
h
Data input
hold time
SPI mode (SITP[1:0]=01),
External clock mode
(SPICKSEL[1:0] = 0)
1- -
T
Manchester
Manchester
data period
(recovered
clock period)
Manchester mode (SITP[1:0]
= 10 or 11),
Internal clock mode
(SPICKSEL[1:0] ≠ 0)
(CKOUT
DIV+1)
ₓ
T
DFSDMCLK
-
(2
ₓ CKOUTDIV)
ₓ T
DFSDMCLK
1. Data based on characterization results, not tested in production.
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