Datasheet

DocID028087 Rev 4 137/193
STM32F412xE/G Electrical characteristics
161
Equation 1: R
AIN
max formula
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of
sampling periods defined in the ADC_SMPR1 register.
f
S
(2)
Sampling rate
(f
ADC
= 30 MHz, and
t
S
= 3 ADC cycles)
12-bit resolution
Single ADC
- - 2 Msps
12-bit resolution
Interleave Dual ADC
mode
- - 3.75 Msps
12-bit resolution
Interleave Triple ADC
mode
- - 6 Msps
I
VREF+
(2)
ADC V
REF
DC current
consumption in conversion
mode
- - 300 500 µA
I
VDDA
(2)
ADC V
DDA
DC current
consumption in conversion
mode
--1.61.8mA
1. V
DDA
minimum value of 1.7 V is possible with the use of an external power supply supervisor (refer to Section 3.18.2:
Internal reset OFF).
2. Guaranteed by characterization, not tested in production.
3. V
REF+
is internally connected to V
DDA
and V
REF-
is internally connected to V
SSA
.
4. R
ADC
maximum value is given for V
DD
=1.7 V, and minimum value for V
DD
=3.3 V.
5. For external triggers, a delay of 1/f
PCLK2
must be added to the latency specified in Table 71.
Table 71. ADC characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 72. ADC accuracy at f
ADC
= 18 MHz
(1)
1. Better performance could be achieved in restricted V
DD
, frequency and temperature ranges.
Symbol Parameter Test conditions Typ Max
(2)
2. Guaranteed by characterization, not tested in production.
Unit
ET Total unadjusted error
f
ADC
=18 MHz
V
DDA
= 1.7 to 3.6 V
V
REF
= 1.7 to 3.6 V
V
DDA
− V
REF
< 1.2 V
±3 ±4
LSB
EO Offset error ±2 ±3
EG Gain error ±1 ±3
ED Differential linearity error ±1 ±2
EL Integral linearity error ±2 ±3
R
AIN
k0.5–()
f
ADC
C
ADC
2
N 2+
()ln××
---------------------------------------------------------------- R
ADC
–=
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