Datasheet

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STM32F412xE/G Electrical characteristics
161
I
2
S interface characteristics
Unless otherwise specified, the parameters given in Table 6 5 for the I
2
S interface are
derived from tests performed under the ambient temperature, f
PCLKx
frequency and V
DD
supply voltage conditions summarized in Table 15, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (CK, SD, WS).
Note: Refer to the I2S section of RM0383 reference manual for more details on the sampling
frequency (F
S
).
f
MCK
, f
CK
, and D
CK
values reflect only the digital peripheral behavior. The values of these
parameters might be slightly impacted by the source clock precision. D
CK
depends mainly
on the value of ODD bit. The digital contribution leads to a minimum value of
(I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). F
S
maximum value is supported for each mode/condition.
Table 65. I
2
S dynamic characteristics
(1)
Symbol Parameter Conditions Min Max Unit
f
MCK
I2S Main clock output - 256x8K 256xFs
(2)
MHz
f
CK
I2S clock frequency
Master data: 32 bits - 64xFs
MHz
Slave data: 32 bits - 64xFs
D
CK
I2S clock frequency duty cycle Slave receiver 30 70 %
t
v(WS)
WS valid time Master mode - 5
ns
t
h(WS)
WS hold time Master mode 0 -
t
su(WS)
WS setup time Slave mode 2 -
t
h(WS)
WS hold time Slave mode 0.5 -
t
su(SD_MR)
Data input setup time
Master receiver 0 -
t
su(SD_SR)
Slave receiver 2 -
t
h(SD_MR)
Data input hold time
Master receiver 0 -
t
h(SD_SR)
Slave receiver 2.5 -
t
v(SD_ST)
Data output valid time
Slave transmitter (after enable edge) - 15
t
v(SD_MT)
Master transmitter (after enable edge) - 2.5
t
h(SD_ST)
Data output hold time
Slave transmitter (after enable edge) 6 -
t
h(SD_MT)
Master transmitter (after enable edge) 0 -
1. Guaranteed by characterization, not tested in production.
2. The maximum value of 256xFs is 50 MHz (APB1 maximum frequency).
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