Datasheet

Electrical characteristics STM32F412xE/G
128/193 DocID028087 Rev 4
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 6 4 for the SPI interface are
derived from tests performed under the ambient temperature, f
PCLKx
frequency and V
DD
supply voltage conditions summarized in Table 15, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 64. SPI dynamic characteristics
(1)
Symbol Parameter Conditions Min Typ Max Unit
f
SCK
1/t
c(SCK)
SPI clock frequency
Master full duplex/receiver mode,
2.7 V < V
DD
< 3.6 V
SPI1/4/5
--50
MHz
Master transmitter mode
1.7 V < V
DD
< 3.6 V
SPI1/4/5
--
50
Master mode
1.7 V < V
DD
< 3.6 V
SPI1/2/3/4/5
--
25
Slave transmitter/full duplex mode
2.7 V < V
DD
< 3.6 V
SPI1//4/5
--
50
Slave transmitter/full duplex mode
1.7 V < V
DD
< 3.6 V
SPI1/4/5
--
35
(2)
Slave receiver mode,
1.7 V < V
DD
< 3.6 V
SPI1/4/5
--50
Slave mode,
1.7 V < V
DD
< 3.6 V
SPI2/3
--
25
Duty(SCK)
Duty cycle of SPI clock
frequency
Slave mode 30 50 70 %
t
w(SCKH)
t
w(SCKL)
SCK high and low time Master mode, SPI presc = 2 T
PCLK
−1.5
T
PCLK
T
PCLK
+1.5
ns
t
su(NSS)
NSS setup time Slave mode, SPI presc = 2 3T
PCLK
--ns
t
h(NSS)
NSS hold time Slave mode, SPI presc = 2 2T
PCLK
--ns
t
su(MI)
Data input setup time
Master mode 4.5 - - ns
t
su(SI)
Slave mode 1.5 - - ns
t
h(MI)
Data input hold time
Master mode 5 - - ns
t
h(SI)
Slave mode 0.5 - - ns
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