Datasheet

ManualsBrandsST ManualsEmbedded Processors & ControllersMicrocontroller 32bit 512KB LQFP

This is information on a product in full production.

May 2016 DocID028087 Rev 4 1/193

STM32F412xE STM32F412xG

ARM

-Cortex

-M4 32b MCU+FPU, 125 DMIPS, 1MB Flash,

256KB RAM, USB OTG FS, 17 TIMs, 1 ADC, 17 comm. interfaces

Datasheet - production data

Features

• Dynamic Efficiency Line with BAM (Batch

Acquisition Mode)

• Core: ARM

32-bit Cortex

-M4 CPU with

FPU, Adaptive real-time accelerator (ART

Accelerator™) allowing 0-wait state execution

from Flash memory, frequency up to 100 MHz,

memory protection unit,

125 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1),

and DSP instructions

• Memories

– Up to 1 Mbyte of Flash memory

– 256 Kbyte of SRAM

– Flexible external static memory controller

with up to 16-bit data bus: SRAM, PSRAM,

NOR Flash memory

– Dual mode Quad-SPI interface

• LCD parallel interface, 8080/6800 modes

• Clock, reset and supply management

– 1.7 V to 3.6 V application supply and I/Os

– POR, PDR, PVD and BOR

– 4-to-26 MHz crystal oscillator

– Internal 16 MHz factory-trimmed RC

– 32 kHz oscillator for RTC with calibration

– Internal 32 kHz RC with calibration

• Power consumption

– Run: 112 µA/MHz (peripheral off)

– Stop (Flash in Stop mode, fast wakeup

time): 50 µA Typ @ 25 °C; 75 µA max

@25 °C

– Stop (Flash in Deep power down mode,

slow wakeup time): down to 18 µA @

25 °C; 40 µA max @25 °C

– Standby: 2.4 µA @25 °C / 1.7 V without

RTC; 12 µA @85 °C @1.7 V

–V

BAT

supply for RTC: 1 µA @25 °C

• 1×12-bit, 2.4 MSPS ADC: up to 16 channels

• 2x digital filters for sigma delta modulator,

4x PDM interfaces, stereo microphone support

• General-purpose DMA: 16-stream DMA

• Up to 17 timers: up to twelve 16-bit timers, two

32-bit timers up to 100 MHz each with up to

four IC/OC/PWM or pulse counter and

quadrature (incremental) encoder input, two

watchdog timers (independent and window),

one SysTick timer

• Debug mode

– Serial wire debug (SWD) & JTAG

–Cortex



-M4 Embedded Trace Macrocell™

• Up to 114 I/O ports with interrupt capability

– Up to 109 fast I/Os up to 100 MHz

– Up to 114 five V-tolerant I/Os

• Up to 17 communication interfaces

–Up to 4x I

C interfaces (SMBus/PMBus)

– Up to 4 USARTs (2 x 12.5 Mbit/s,

2 x 6.25 Mbit/s), ISO 7816 interface, LIN,

IrDA, modem control)

– Up to 5 SPI/I2Ss (up to 50 Mbit/s, SPI or

I2S audio protocol), out of which 2 muxed

full-duplex I2S interfaces

– SDIO interface (SD/MMC/eMMC)

– Advanced connectivity: USB 2.0 full-speed

device/host/OTG controller with PHY

– 2x CAN (2.0B Active)

• True random number generator

• CRC calculation unit

• 96-bit unique ID

• RTC: subsecond accuracy, hardware calendar

• All packages are ECOPACK

Table 1. Device summary

Reference Part number

STM32F412xE

STM32F412CE, STM32F412RE, STM32F412VE,

STM32F412ZE

STM32F412xG

STM32F412CG, STM32F412RG, STM32F412VG,

STM32F412ZG

WLCSP64

)%*$

UFQFPN48

(7x7 mm)

UFBGA100

(7x7mm)

UFBGA144

(10x10mm)

(3.623x3.651mm)

LQFP100 (14x14mm)

LQFP144 (20x20mm)

LQFP64 (10x10mm)

www.st.com

Downloaded from Arrow.com.

Summary of content (193 pages)

PAGE 1
STM32F412xE STM32F412xG ARM®-Cortex®-M4 32b MCU+FPU, 125 DMIPS, 1MB Flash, 256KB RAM, USB OTG FS, 17 TIMs, 1 ADC, 17 comm. interfaces Datasheet - production data Features )%*$ • Dynamic Efficiency Line with BAM (Batch Acquisition Mode) ® ® • Core: ARM 32-bit Cortex -M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 100 MHz, memory protection unit, 125 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.
PAGE 2
Contents STM32F412xE/G Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 ARM® Cortex®-M4 with FPU core with embedded Flash and SRAM . . . 19 3.2 Adaptive real-time memory accelerator (ART Accelerator™) . .
PAGE 3
STM32F412xE/G Contents 3.22 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.23 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.23.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.23.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.23.3 Basic timer (TIM6, TIM7) . . . . . . . . . . . . . .
PAGE 4
Contents 7 4/193 Downloaded from Arrow.com. STM32F412xE/G 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.
PAGE 5
STM32F412xE/G Contents 7.4 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 7.5 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 7.6 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 7.7 UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 6
List of tables STM32F412xE/G List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. 6/193 Downloaded from Arrow.com. Device summary . . . . . . .
PAGE 7
STM32F412xE/G Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90.
PAGE 8
List of tables Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. 8/193 Downloaded from Arrow.com. STM32F412xE/G Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 9
STM32F412xE/G List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43.
PAGE 10
List of figures Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. 10/193 Downloaded from Arrow.
PAGE 11
STM32F412xE/G Figure 87. List of figures Display application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 DocID028087 Rev 4 11/193 11 Downloaded from Arrow.com.
PAGE 12
Introduction 1 STM32F412xE/G Introduction This datasheet provides the description of the STM32F412xE/G microcontrollers. For information on the Cortex®-M4 core, refer to the Cortex®-M4 programming manual (PM0214) available from www.st.com. 12/193 Downloaded from Arrow.com.
PAGE 13
STM32F412xE/G 2 Description Description The STM32F412XE/G devices are based on the high-performance ARM® Cortex® -M4 32bit RISC core operating at a frequency of up to 100 MHz. Their Cortex®-M4 core features a Floating point unit (FPU) single precision which supports all ARM single-precision dataprocessing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.
PAGE 14
Description STM32F412xE/G These features make the STM32F412xE/G microcontrollers suitable for a wide range of applications: • Motor drive and application control • Medical equipment • Industrial applications: PLC, inverters, circuit breakers • Printers, and scanners • Alarm systems, video intercom, and HVAC • Home audio appliances • Mobile phone sensor hub • Wearable devices • Connected objects • Wifi modules Figure 4 shows the general block diagram of the devices.
PAGE 15
STM32F412xE/G Description Table 2.
PAGE 16
Description 2.1 STM32F412xE/G Compatibility with STM32F4 series The STM32F412xE/G are fully software and feature compatible with the STM32F4 series (STM32F42x, STM32F401, STM32F43x, STM32F41x, STM32F405 and STM32F407) The STM32F412xE/G can be used as drop-in replacement of the other STM32F4 products but some slight changes have to be done on the PCB board. Figure 1. Compatible board design for LQFP100 package 3% QRW DYDLODEOH DQ\PRUH 5HSODFHG E\ 9 &$3B
PAGE 17
STM32F412xE/G Description Figure 2. Compatible board design for LQFP64 package 670 ) [[ 670 ) [[ 670 ) [[ 670 ) [[ 670 ) [[ 9'' 9&$3B 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 9'' 966 3% QRW DYDLODEOH DQ\PRUH 5HSODFHG E\ 9&$3B 9'' 966 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 9'' 966 3% 3% 9&$3B 966 9'' 3% 3% 3% 9&$3B 9''
PAGE 18
Description STM32F412xE/G Figure 4. STM32F412xE/G block diagram (70 )60& 125 )ODVK 65$0 365$0 $+% 038 )38 , %86 $50 &RUWH[ 0 &RUWH[ 0 0+] &/. 1(> @ $> @ '> @ 12(1 1:(1 1%/> @ 1:$,7 &/. &6$ &6% '> @ 4XDG 63, 19,& .% 65$0 ' %86 6 %86 $&&(/ &$&+( -7$* 6: $+% EXV PDWUL[ 6 0 -7567 -7', -7&. 6:&/. -7'2 6:' -7'2 75$&(&/. 75$&('> @ 8S WR 0% )ODVK PHPRU\ 51* ),)2 *3,2 3257 $ 3%> @ *3,2 3257 % $+% 0+] 6WUHDPV '0$ 3$> @ ),)2 6W
PAGE 19
STM32F412xE/G Functional overview 3 Functional overview 3.1 ARM® Cortex®-M4 with FPU core with embedded Flash and SRAM The ARM® Cortex®-M4 with FPU processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
PAGE 20
Functional overview 3.4 STM32F412xE/G Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 byte and the whole 4 Gbyte of addressable memory.
PAGE 21
STM32F412xE/G 3.8 Functional overview Embedded SRAM All devices embed 256 Kbyte of system SRAM which can be accessed (read/write) at CPU clock speed with 0 wait states 3.9 Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves (Flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. Figure 5.
PAGE 22
Functional overview STM32F412xE/G The DMA can be used with the main peripherals: 3.11 • SPI and I2S • I2C and I2CFMP • USART • General-purpose, basic and advanced-control timers TIMx • SD/SDIO/MMC/eMMC host interface • Quad-SPI • ADC • Digital Filter for sigma-delta modulator (DFSDM) with a separate stream for each filter. Flexible static memory controller (FSMC) The Flexible static memory controller (FSMC) includes a NOR/PSRAM memory controller.
PAGE 23
STM32F412xE/G 3.13 Functional overview Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-M4 with FPU.
PAGE 24
Functional overview 3.16 STM32F412xE/G Boot modes At startup, boot pins are used to select one out of three boot options: • Boot from user Flash memory • Boot from system memory • Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory by using one of the interface listed in the Table 3 or the USB OTG FS in device mode through DFU (device firmware upgrade). Table 3.
PAGE 25
STM32F412xE/G Functional overview it is independent from VDD or VDDA but it must be the last supply to be provided and the first to disappear. The following conditions VDDUSB must be respected: – During power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than VDD – During power-down phase (VDD < VDD_MIN), VDDUSB should be always lower than VDD – VDDUSB rising and falling time rate specifications must be respected.
PAGE 26
Functional overview STM32F412xE/G 3.18 Power supply supervisor 3.18.1 Internal reset ON This feature is available for VDD operating voltage range 1.8 V to 3.6 V. On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other package, the power supply supervisor is always enabled. The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry.
PAGE 27
STM32F412xE/G Functional overview Figure 7. Power supply supervisor interconnection with internal reset OFF(1) 9'' ([WHUQDO 9'' SRZHU VXSSO\ VXSHUYLVRU ([W UHVHW FRQWUROOHU DFWLYH ZKHQ 9'' 9 1567 3'5B21 9'' 06Y 9 1. The PRD_ON pin is available only on WLCSP64, UFBGA100, UFBGA144 and LQFP144 packages. A comprehensive set of power-saving mode allows to design low-power applications. When the internal reset is OFF, the following integrated features are no longer supported: 3.
PAGE 28
Functional overview STM32F412xE/G There are three power modes configured by software when the regulator is ON: • MR is used in the nominal regulation mode (With different voltage scaling in Run mode) In Main regulator mode (MR mode), different voltage scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. • LPR is used in the Stop mode The LP regulator mode is configured by software when entering Stop mode. • Power-down is used in Standby mode.
PAGE 29
STM32F412xE/G Functional overview Figure 8. Regulator OFF 9 ([WHUQDO 9&$3B SRZHU $SSOLFDWLRQ UHVHW VXSSO\ VXSHUYLVRU ([W UHVHW FRQWUROOHU DFWLYH VLJQDO RSWLRQDO ZKHQ 9&$3B 0LQ 9 9'' 3$ 9'' 1567 %<3$66B5(* 9 9&$3B 9&$3B DL 9 The following conditions must be respected: Note: • VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains.
PAGE 30
Functional overview STM32F412xE/G Figure 9. Startup in regulator OFF: slow VDD slope power-down reset risen after VCAP_1/VCAP_2 stabilization 9'' 3'5 9 9 0LQ 9 9&$3B 9&$3B WLPH 1567 3$ WLPH 06Y 9 1. This figure is valid whatever the internal reset mode (ON or OFF). Figure 10. Startup in regulator OFF mode: fast VDD slope power-down reset risen before VCAP_1/VCAP_2 stabilization 9'' 3'5 9 9&$3B 9&$3B 9 0LQ 9 1567 WLPH 3$ DVVHUWHG H[WHUQDOO\ WLPH 1.
PAGE 31
STM32F412xE/G 3.19.3 Functional overview Regulator ON/OFF and internal reset ON/OFF availability Table 4.
PAGE 32
Functional overview STM32F412xE/G Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date. The RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or from the VBAT pin. 3.
PAGE 33
STM32F412xE/G 3.23 Functional overview Timers and watchdogs The devices embed two advanced-control timer, ten general-purpose timers, two basic timers, two watchdog timers and one SysTick timer. All timer counters can be frozen in debug mode. Table 5 compares the features of the advanced-control and general-purpose timers. DocID028087 Rev 4 33/193 42 Downloaded from Arrow.com.
PAGE 34
Functional overview STM32F412xE/G Table 5.
PAGE 35
STM32F412xE/G 3.23.1 Functional overview Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1/8) can be seen as three-phase PWM generator multiplexed on 4 independent channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete generalpurpose timers.
PAGE 36
Functional overview 3.23.4 STM32F412xE/G Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. 3.23.
PAGE 37
STM32F412xE/G 3.25 Functional overview Universal synchronous/asynchronous receiver transmitters (USART) The devices embed four universal synchronous/asynchronous receiver transmitters (USART1, USART2, USART3 and USART6). These four interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. USART1 and USART6 interfaces are able to communicate at speeds of up to 12.5 Mbit/s.
PAGE 38
Functional overview 3.27 STM32F412xE/G Inter-integrated sound (I2S) Five standard I2S interfaces (multiplexed with SPI1 to SPI5) are available. They can be operated in master or slave mode, in simplex communication mode, and full duplex mode for I2S2 and I2S3. All I2S interfaces can be configured to operate with a 16-/32-bit resolution as an input or output channel. I2Sx audio sampling frequencies from 8 kHz up to 192 kHz are supported.
PAGE 39
STM32F412xE/G Functional overview The DFSDM peripheral supports: • • 4 multiplexed input digital serial channels: – configurable SPI interface to connect various SD modulator(s) – configurable Manchester coded 1 wire interface support – PDM (Pulse Density Modulation) microphone input support – maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding) – clock output for SD modulator(s): 0...
PAGE 40
Functional overview 3.30 STM32F412xE/G Secure digital input/output interface (SDIO) An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory Card Specification Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit.
PAGE 41
STM32F412xE/G 3.33 Functional overview Random number generator (RNG) All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 3.34 General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function.
PAGE 42
Functional overview 3.38 STM32F412xE/G Embedded Trace Macrocell™ The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F412xE/G through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using any high-speed channel available.
PAGE 43
STM32F412xE/G 4 Pinouts and pin description Pinouts and pin description Figure 11.
PAGE 44
Pinouts and pin description STM32F412xE/G 9%$7 3& 3& 26& B,1 3% 3% %227 3% 3% 3% 3% 3% 3' 3& 3& 3& 3$ 3$ /4)3 9'' 966 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 3$ 966 9'' 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3% 9&$3B 966 9'' 3& 26& B287 3+ 26&B,1 3+ 26&B
PAGE 45
STM32F412xE/G Pinouts and pin description 6$$ 633 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 14.
PAGE 46
Pinouts and pin description STM32F412xE/G 9'' 3'5B21 3( 3( 3% 3% %227 3% 3% 3% 3% 3% 3* 9'' 966 3* 3* 3* 3* 3* 3* 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$ Figure 15.
PAGE 47
STM32F412xE/G Pinouts and pin description Figure 16. STM32F412xE/G UFBGA100 pinout $ 3( 3( 3% % 3( 3( & 3& 3' 3% 3% 3$ 3$ 3$ 3$ 3' 3' 3' 3' 3& 3& 3$ 3' 3' 3& 9&$3 B 3$ 966 3$ 3$ 3& %<3$66 B5(* 3& 3& 3& 966 966 966 3+ 26&B 287 9'' 9'' 9'' + 3& 1567 3'5 B21 3' 3' 3' - 966$ 3& 3& 3' 3' 3' .
PAGE 48
Pinouts and pin description STM32F412xE/G Figure 17.
PAGE 49
STM32F412xE/G Pinouts and pin description Table 9.
PAGE 50
Pinouts and pin description STM32F412xE/G Table 9.
PAGE 51
STM32F412xE/G Pinouts and pin description Table 9.
PAGE 52
Pinouts and pin description STM32F412xE/G Table 9.
PAGE 53
STM32F412xE/G Pinouts and pin description Table 9.
PAGE 54
Pinouts and pin description STM32F412xE/G Table 9.
PAGE 55
STM32F412xE/G Pinouts and pin description Table 9.
PAGE 56
Pinouts and pin description STM32F412xE/G Table 9.
PAGE 57
STM32F412xE/G Pinouts and pin description Table 9.
PAGE 58
Pinouts and pin description STM32F412xE/G Table 9.
PAGE 59
STM32F412xE/G Pinouts and pin description Table 9.
PAGE 60
Pinouts and pin description STM32F412xE/G Table 9.
PAGE 61
Downloaded from Arrow.com.
PAGE 62
/193 Downloaded from Arrow.com.
PAGE 63
Downloaded from Arrow.com.
PAGE 64
/193 Downloaded from Arrow.com.
PAGE 65
Downloaded from Arrow.com.
PAGE 66
/193 Downloaded from Arrow.com.
PAGE 67
DocID028087 Rev 4 Downloaded from Arrow.com.
PAGE 68
Memory mapping 5 STM32F412xE/G Memory mapping The memory map is shown in Figure 18. Figure 18. Memory map 5HVHUYHG &RUWH[½ 0 LQWHUQDO SHULSKHUDOV 5HVHUYHG [( [)))) )))) [( [( ) )))) [$ ± '))) ))) [$ ))) $+% [ [ ))) )))) $+% 5HVHUYHG [)))) )))) 0E\WH EORFN LQWHUQDO 3HULSKHUDOV [ [ [ ))) )))) [ )) $+% [( ['))) )))) 0E\WH EORFN 1RW XVHG [& [%))) )))) 5HVHUYHG 5HVHUYHG [
PAGE 69
STM32F412xE/G Memory mapping Table 11.
PAGE 70
Memory mapping STM32F412xE/G Table 11. STM32F412xE/G register boundary addresses (continued) Bus APB2 70/193 Downloaded from Arrow.com.
PAGE 71
STM32F412xE/G Memory mapping Table 11.
PAGE 72
Electrical characteristics STM32F412xE/G 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
PAGE 73
STM32F412xE/G 6.1.6 Electrical characteristics Power supply scheme Figure 21. Power supply scheme 9%$7 9%$7 WR 9 *3,2V î ) 9''B86% 9&$3B 9&$3B 9'' 966 î Q) î ) ,2 /RJLF .HUQHO ORJLF &38 GLJLWDO 5$0 9ROWDJH UHJXODWRU %<3$66B5(* 9''86% Q) ) 3'5B21 9'' )ODVK PHPRU\ 27* )6 3+< 5HVHW FRQWUROOHU 9''$ 95() Q) ) ,1 /HYHO VKLIWHU 287 9'' %DFNXS FLUFXLWU\ 26& .
PAGE 74
Electrical characteristics 6.1.7 STM32F412xE/G Current consumption measurement Figure 22. Current consumption measurement scheme ,''B9%$7 9%$7 ,'' 9'' 9''$ DL 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 12: Voltage characteristics, Table 13: Current characteristics, and Table 14: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied.
PAGE 75
STM32F412xE/G Electrical characteristics Table 13. Current characteristics Symbol Ratings Max.
PAGE 76
Electrical characteristics STM32F412xE/G 6.3 Operating conditions 6.3.1 General operating conditions Table 15.
PAGE 77
STM32F412xE/G Electrical characteristics Table 15.
PAGE 78
Electrical characteristics STM32F412xE/G Table 16. Features depending on the operating power supply range Operating power supply range ADC operation VDD =1.7 to 2.1 V(4) Conversion time up to 1.2 Msps VDD = 2.1 to 2.4 V Conversion time up to 1.2 Msps VDD = 2.4 to 2.7 V Conversion time up to 2.4 Msps VDD = 2.7 to 3.6 V(6) Conversion time up to 2.
PAGE 79
STM32F412xE/G 6.3.2 Electrical characteristics VCAP_1/VCAP_2 external capacitors Stabilization for the main regulator is achieved by connecting the external capacitor CEXT to the VCAP_1 and VCAP_2 pins. For packages supporting only 1 VCAP pin, the 2 CEXT capacitors are replaced by a single capacitor. CEXT is specified in Table 17. Figure 23. External capacitor CEXT & (65 5 /HDN 06 9 1. Legend: ESR is the equivalent series resistance. Table 17.
PAGE 80
Electrical characteristics 6.3.4 STM32F412xE/G Operating conditions at power-up / power-down (regulator OFF) Subject to general operating conditions for TA. Table 19. Operating conditions at power-up / power-down (regulator OFF)(1) Symbol tVDD tVCAP Parameter Conditions Min Max VDD rise time rate Power-up 20 ∞ VDD fall time rate Power-down 20 ∞ VCAP_1 and VCAP_2 rise time rate Power-up 20 ∞ VCAP_1 and VCAP_2 fall time rate Power-down 20 ∞ Unit µs/V 1.
PAGE 81
STM32F412xE/G Electrical characteristics Table 20. Embedded reset and power control block characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit - - 40 - mV Falling edge 2.13 2.19 2.24 Rising edge 2.23 2.29 2.33 Brownout level 2 threshold Falling edge 2.44 2.50 2.56 Rising edge 2.53 2.59 2.63 Brownout level 3 threshold Falling edge 2.75 2.83 2.88 Rising edge 2.85 2.92 2.
PAGE 82
Electrical characteristics STM32F412xE/G Typical and maximum current consumption The MCU is placed under the following conditions: • All I/O pins are in input mode with a static value at VDD or VSS (no load). • All peripherals are disabled except if it is explicitly mentioned. • The Flash memory access time is adjusted to both fHCLK frequency and VDD ranges (refer to Table 16: Features depending on the operating power supply range).
PAGE 83
STM32F412xE/G Electrical characteristics Table 22. Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 3.
PAGE 84
Electrical characteristics STM32F412xE/G Table 23. Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory- VDD = 1.
PAGE 85
STM32F412xE/G Electrical characteristics Table 24. Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory - VDD = 3.
PAGE 86
Electrical characteristics STM32F412xE/G Table 25. Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory - VDD = 3.
PAGE 87
STM32F412xE/G Electrical characteristics Table 26. Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory - VDD = 1.
PAGE 88
Electrical characteristics STM32F412xE/G Table 27. Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled with prefetch) running from Flash memory - VDD = 3.
PAGE 89
STM32F412xE/G Electrical characteristics Table 28. Typical and maximum current consumption in Sleep mode - VDD = 3.
PAGE 90
Electrical characteristics STM32F412xE/G 2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register). 3. Tested in production. Table 29. Typical and maximum current consumption in Sleep mode - VDD = 1.
PAGE 91
STM32F412xE/G Electrical characteristics Table 29. Typical and maximum current consumption in Sleep mode - VDD = 1.7 V (continued) Symbol Parameter fHCLK (MHz) Conditions TA = 25 °C TA = 25 °C TA = 85 °C TA = 105 °C 100 2.9 3.51 4.14 4.90 84 2.4 2.83 3.46 4.16 64 1.7 2.08 2.59 3.18 50 1.4 1.77 2.23 2.84 25 1.0 1.37 1.88 2.50 20 1.3 1.37 1.88 2.50 16 0.5 0.63 1.23 1.91 1 0.4 0.52 1.13 1.81 100 3.3 3.22 3.98 4.90 84 2.8 2.62 3.30 4.16 64 2.1 1.
PAGE 92
Electrical characteristics STM32F412xE/G Table 31. Typical and maximum current consumption in Stop mode - VDD=3.6 V Max(1) Typ Symbol Conditions Parameter Flash in Stop mode, all oscillators OFF, no independent watchdog TA = 25 °C TA = 25 °C TA = 85 °C TA = 105 °C Main regulator usage 124.0 179.0(2) 907.2 1762.0(2) Low power regulator usage 52.8 104.9(2) 773.8 IDD_STOP Flash in Deep power Main regulator usage 87.6 down mode, all oscillators Low power regulator usage 26.
PAGE 93
STM32F412xE/G Electrical characteristics Table 34. Typical and maximum current consumptions in VBAT mode Max(2) Typ Symbol TA = TA = 85 °C 105 °C Unit TA = 25 °C Conditions(1) Parameter VBAT = VBAT= VBAT = VBAT = VBAT = 3.6 V 1.7 V 2.4 V 3.3 V 3.6 V Low-speed oscillator (LSE in lowdrive mode) and RTC ON Backup IDD_VBAT domain supply Low-speed oscillator (LSE in highcurrent drive mode) and RTC ON RTC and LSE OFF 0.74 0.87 1.04 1.11 3.0 5.0 1.52 1.70 1.97 2.09 3.8 5.8 0.04 0.04 0.
PAGE 94
Electrical characteristics STM32F412xE/G Figure 25. Typical VBAT current consumption (LSE and RTC ON/LSE oscillator “high drive” mode selection) 9 ,''B9%$7 $ 9 9 9 9 9 9 9 9 7HPSHUDWXUH & 06 9 I/O system current consumption The current consumption of the I/O system has two components: static and dynamic.
PAGE 95
STM32F412xE/G Electrical characteristics pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DD × f SW × C where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDD is the MCU supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.
PAGE 96
Electrical characteristics STM32F412xE/G Table 35. Switching output I/O current consumption Symbol Parameter Conditions(1) VDD = 3.3 V C = CINT VDD = 3.3 V CEXT = 0 pF C = CINT + CEXT + CS IDDIO I/O switching current VDD = 3.3 V CEXT =10 pF C = CINT + CEXT + CS VDD = 3.3 V CEXT = 22 pF C = CINT + CEXT + CS VDD = 3.3 V CEXT = 33 pF C = CINT + CEXT + CS I/O toggling Typ frequency (fSW) 2 MHz 0.05 8 MHz 0.15 25 MHz 0.45 50 MHz 0.85 60 MHz 1.00 84 MHz 1.40 90 MHz 1.67 2 MHz 0.
PAGE 97
STM32F412xE/G Electrical characteristics On-chip peripheral current consumption The MCU is placed under the following conditions: • At startup, all I/O pins are in analog input configuration. • All peripherals are disabled unless otherwise mentioned. • The ART accelerator is ON. • Voltage Scale 2 mode selected, internal digital voltage V12 = 1.26 V. • HCLK is the system clock at 100 MHz. fPCLK1 = fHCLK/2, and fPCLK2 = fHCLK.
PAGE 98
Electrical characteristics STM32F412xE/G Table 36. Peripheral current consumption (continued) IDD (Typ) Peripheral APB1 98/193 Downloaded from Arrow.com. Unit Scale 1 Scale 2 Scale 3 AHB-APB1 bridge 1.10 1.00 0.94 TIM2 13.62 12.95 11.59 TIM3 10.56 10.05 8.97 TIM4 10.72 10.21 9.12 TIM5 13.46 12.83 11.47 TIM6 2.92 2.79 2.47 TIM7 2.72 2.60 2.31 TIM12 6.22 5.93 5.28 TIM13 4.70 4.48 3.97 TIM14 4.60 4.38 3.91 WWDG 1.76 1.67 1.47 SPI2/I2S2 4.04 3.83 3.
PAGE 99
STM32F412xE/G Electrical characteristics Table 36. Peripheral current consumption (continued) IDD (Typ) Peripheral APB2 Unit Scale 1 Scale 2 Scale 3 AHB-APB2 bridge 0.09 0.07 0.08 TIM1 6.83 6.46 5.81 TIM8 6.63 6.29 5.63 USART1 3.31 3.11 2.80 USART6 3.21 3.02 2.73 ADC1 3.51 3.31 2.98 SDIO 3.74 3.51 3.17 SPI1 1.47 1.36 1.23 SPI4 1.56 1.45 1.31 SYSCFG 0.54 0.49 0.45 TIM9 3.09 2.92 2.63 TIM10 1.91 1.79 1.61 TIM11 1.93 1.81 1.64 SPI5 1.54 1.44 1.
PAGE 100
Electrical characteristics STM32F412xE/G Figure 26. Low-power mode wakeup :DNHXS IURP 6WRS PRGH PDLQ UHJXODWRU 2SWLRQ E\WHV DUH QRW UHORDGHG &38 UHVWDUW 5HJXODWRU +6, UHVWDUW )ODVK VWRS H[LW UDPS XS :DNHXS IURP 6WRS PRGH PDLQ UHJXODWRU IODVK LQ 'HHS SRZHU GRZQ PRGH 2SWLRQ E\WHV DUH QRW UHORDGHG &38 UHVWDUW 5HJXODWRU +6, UHVWDUW )ODVK 'HHS 3G UHFRYHU\ UDPS XS :DNHXS IURP 6WRS UHJXODWRU LQ ORZ SRZHU PRGH 2SWLRQ E\WHV DUH QRW UHORDGHG 5HJXODWRU UDPS XS &38 UHVWDUW +6, UHVWDUW )ODVK VWRS H[L
PAGE 101
STM32F412xE/G Electrical characteristics Table 37. Low-power mode wakeup timings(1) (continued) Symbol Conditions Min(1) Typ(1) Max(1) Main regulator - 12.9 15.0 Main regulator, Flash memory in Deep power down mode - 104.9 120.0 Wakeup from Stop mode, regulator in low power mode(2) - 20.8 28.0 Regulator in low power mode, Flash memory in Deep power down mode(2) - 112.9 130.0 Main regulator with Flash in Stop mode or Deep power down - 4.9 7.
PAGE 102
Electrical characteristics STM32F412xE/G Table 38. High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit 1 - 50 MHz fHSE_ext External user clock source frequency(1) VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD VHSEL OSC_IN input pin low level voltage VSS - 0.
PAGE 103
STM32F412xE/G Electrical characteristics Figure 27. High-speed external clock source AC timing diagram 6(3%( 6(3%, TR (3% TF (3% T7 (3% /3#?). ), T7 (3% T 4(3% %XTERNAL CLOCK SOURCE F(3%?EXT 34- & AI Figure 28.
PAGE 104
Electrical characteristics STM32F412xE/G Table 40. HSE 4-26 MHz oscillator characteristics(1) Symbol fOSC_IN RF IDD Parameter Conditions Min Typ Max Unit Oscillator frequency 4 - 26 MHz Feedback resistor - 200 - kΩ VDD=3.3 V, ESR= 30 Ω, CL=5 pF @25 MHz - 450 - VDD=3.
PAGE 105
STM32F412xE/G Electrical characteristics possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). The LSE high-power mode allows to cover a wider range of possible crystals but with a cost of higher power consumption. Table 41. LSE oscillator characteristics (fLSE = 32.
PAGE 106
Electrical characteristics 6.3.9 STM32F412xE/G Internal clock source characteristics The parameters given in Table 42 and Table 43 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 15. High-speed internal (HSI) RC oscillator Table 42. HSI oscillator characteristics (1) L Symbol fHSI Parameter Conditions Min Typ Max Unit Frequency - - 16 - MHz HSI user trimming step(2) - - - 1 % –8 - 4.
PAGE 107
STM32F412xE/G Electrical characteristics Low-speed internal (LSI) RC oscillator Table 43. LSI oscillator characteristics (1) Symbol Parameter fLSI(2) tsu(LSI) Min Typ Max Unit 17 32 47 kHz LSI oscillator startup time - 15 40 µs LSI oscillator power consumption - 0.4 0.6 µA Frequency (3) IDD(LSI)(3) 1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified. 2. Guaranteed by characterization, not tested in production. 3. Guaranteed by design, not tested in production. Figure 32.
PAGE 108
Electrical characteristics 6.3.10 STM32F412xE/G PLL characteristics The parameters given in Table 44 and Table 45 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 15. Table 44. Main PLL characteristics Symbol Parameter Conditions Min Typ Max Unit fPLL_IN PLL input clock(1) - 0.95(2) 1 2.
PAGE 109
STM32F412xE/G Electrical characteristics Table 45. PLLI2S (audio PLL) characteristics Symbol Parameter Conditions Min Typ Max fPLLI2S_IN PLLI2S input clock(1) - 0.95(2) 1 2.10 fPLLI2S_OUT PLLI2S multiplier output clock - - - 216 fVCO_OUT PLLI2S VCO output - 100 - 432 tLOCK PLLI2S lock time VCO freq = 100 MHz 75 - 200 VCO freq = 432 MHz 100 - 300 RMS - 90 - peak to peak - ±280 - Average frequency of 12.
PAGE 110
Electrical characteristics 6.3.11 STM32F412xE/G PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 52: EMI characteristics for LQFP144). It is available only on the main PLL. Table 46. SSCG parameter constraints Symbol Parameter Min Typ Max(1) Unit fMod Modulation frequency - - 10 kHz md Peak modulation depth 0.
PAGE 111
STM32F412xE/G Electrical characteristics Figure 33 and Figure 34 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 33. PLL output clock waveforms in center spread mode &REQUENCY 0,,?/54 MD & MD TMODE 4IME XTMODE AI Figure 34. PLL output clock waveforms in down spread mode )UHTXHQF\ 3//B287 ) [PG WPRGH 7LPH [WPRGH DL E 6.3.
PAGE 112
Electrical characteristics STM32F412xE/G Table 48.
PAGE 113
STM32F412xE/G Electrical characteristics Table 49. Flash memory programming with VPP voltage Symbol Parameter Conditions tprog Double word programming tERASE16KB Sector (16 KB) erase time tERASE64KB Sector (64 KB) erase time tERASE128KB Sector (128 KB) erase time tME Min(1) Typ Max(1) Unit - 16 100(2) µs - 230 - - 490 - - 875 - - 6.9 - s TA = 0 to +40 °C VDD = 3.3 V VPP = 8.5 V Mass erase time ms Vprog Programming voltage - 2.7 - 3.
PAGE 114
Electrical characteristics STM32F412xE/G The test results are given in Table 52. They are based on the EMS levels and classes defined in application note AN1709. Table 51. EMS characteristics for LQFP144 package Symbol Parameter Conditions Level/ Class VFESD VDD = 3.
PAGE 115
STM32F412xE/G Electrical characteristics Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC code, is running. This emission test is compliant with IEC61967-2 standard which specifies the test board and the pin loading. Table 52. EMI characteristics for LQFP144 Symbol Parameter Max vs. [fHSE/fCPU] Monitored frequency band Conditions Unit 8/100 MHz SEMI 6.3.14 Peak level VDD = 3.
PAGE 116
Electrical characteristics STM32F412xE/G Static latchup Two complementary static tests are required on six parts to assess the latchup performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latchup standard. Table 54. Electrical sensitivities Symbol LU 6.3.
PAGE 117
STM32F412xE/G Electrical characteristics Table 55.
PAGE 118
Electrical characteristics STM32F412xE/G Table 56. I/O static characteristics (continued) Symbol Parameter Conditions Min Typ Max 1.7 V≤VDD≤3.6 V 10% VDD(2)(3) - - 0.
PAGE 119
STM32F412xE/G Electrical characteristics Figure 35.
PAGE 120
Electrical characteristics STM32F412xE/G Table 57.
PAGE 121
STM32F412xE/G Electrical characteristics Table 58.
PAGE 122
Electrical characteristics STM32F412xE/G Figure 36. I/O AC characteristics definition (;7(51$/ 287387 21 &/ WU ,2 RXW WI ,2 RXW 7 0D[LPXP IUHTXHQF\ LV DFKLHYHG LI WU WI 7 DQG LI WKH GXW\ F\FOH LV ZKHQ ORDGHG E\ &/ VSHFLILHG LQ WKH WDEOH ³ , 2 $& FKDUDFWHULVWLFV´ 6.3.17 DL G NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 56).
PAGE 123
STM32F412xE/G Electrical characteristics Figure 37. Recommended NRST pin protection 9'' ([WHUQDO UHVHW FLUFXLW 1567 538 ,QWHUQDO 5HVHW )LOWHU ) 670 ) DL F 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 59. Otherwise the reset is not taken into account by the device. 6.3.18 TIM timer characteristics The parameters given in Table 60 are guaranteed by design.
PAGE 124
Electrical characteristics 6.3.19 STM32F412xE/G Communications interfaces I2C interface characteristics The I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” opendrain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 61. Refer also to Section 6.3.
PAGE 125
STM32F412xE/G Electrical characteristics 4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal. 5. The minimum width of the spikes filtered by the analog filter is above tSP (max) Figure 38.
PAGE 126
Electrical characteristics STM32F412xE/G FMPI2C characteristics The following table presents FMPI2C characteristics. Refer also to Section 6.3.16: I/O port characteristics for more details on the input/output function characteristics (SDA and SCL). Table 63. FMPI2C characteristics(1) Standard mode Fast mode Fast+ mode Parameter Unit Min Max Min Max Min Max 2 - 8 - 18 - fFMPI2CC FMPI2CCLK frequency tw(SCLL) SCL clock low time 4.7 - 1.3 - 0.5 - tw(SCLH) SCL clock high time 4.
PAGE 127
STM32F412xE/G Electrical characteristics Figure 39. FMPI2C timing diagram and measurement circuit 9''B, & 9''B, & 53 53 670 )[[ 56 6'$ ,ð& EXV 56 6&/ 67$57 5(3($7(' 67$57 67$57 WVX 67$ 6'$ WI 6'$ WU 6'$ WK 67$ WVX 6'$ WZ 6&/+ WZ 672 67$ 6723 WK 6'$ 6&/ WZ 6&// WU 6&/ WI 6&/ WVX 672 06Y 9 DocID028087 Rev 4 127/193 161 Downloaded from Arrow.com.
PAGE 128
Electrical characteristics STM32F412xE/G SPI interface characteristics Unless otherwise specified, the parameters given in Table 64 for the SPI interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 15, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.
PAGE 129
STM32F412xE/G Electrical characteristics Table 64. SPI dynamic characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit ta(SO) Data output access time Slave mode 7 - 21 ns tdis(SO) Data output disable time Slave mode 5 - 12 ns Slave mode (after enable edge), 2.7 V < VDD < 3.6 V - 7.5 9 ns Slave mode (after enable edge), 1.7 V < VDD < 3.6 V - 7.5 14 ns tv(SO) Data output valid time th(SO) Data output hold time Slave mode (after enable edge), 1.
PAGE 130
Electrical characteristics STM32F412xE/G Figure 41. SPI timing diagram - slave mode and CPHA = 1(1) 166 LQSXW 6&. LQSXW W68 166 &3+$ &32/ &3+$ &32/ WK 166 WF 6&. WZ 6&.+ WZ 6&./ 0,62 287387 06% 287 WU 6&. WI 6&. %,7 287 WGLV 62 /6% 287 WK 6, WVX 6, 026, ,1387 WK 62 WY 62 WD 62 06% ,1 %,7 ,1 /6% ,1 DL E Figure 42. SPI timing diagram - master mode(1) +LJK 166 LQSXW 6&. 2XWSXW &3+$ &32/ 6&. 2XWSXW WF 6&.
PAGE 131
STM32F412xE/G Electrical characteristics I2S interface characteristics Unless otherwise specified, the parameters given in Table 65 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 15, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.
PAGE 132
Electrical characteristics STM32F412xE/G Figure 43. I2S slave timing diagram (Philips protocol)(1) tc(CK) CK Input CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(2) MSB transmit Bitn transmit tsu(SD_SR) LSB receive(2) SDreceive th(SD_ST) LSB transmit th(SD_SR) MSB receive Bitn receive LSB receive ai14881b 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 44.
PAGE 133
STM32F412xE/G Electrical characteristics QSPI interface characteristics Unless otherwise specified, the parameters given in the following tables for QSPI are derived from tests performed under the ambient temperature, fAHB frequency and VDD supply voltage conditions summarized in Table 15, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C=20pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.
PAGE 134
Electrical characteristics STM32F412xE/G Table 67. QSPI dynamic characteristics in DDR mode(1) (continued) Symbol Parameter Conditions QSPI clock high and low - ts(IN) Data input setup time th(IN) Data input hold time tv(OUT) Data output valid time th(OUT) Data output hold time tw(CKH) tw(CKL) Min Typ Max Unit (T(CK) / 2)-1 - T(CK) / 2 T(CK) / 2) - (T(CK) / 2)+1 - 0 - - - 4 - - 2.7 V
PAGE 135
STM32F412xE/G Electrical characteristics 2. The USB OTG FS functionality is ensured down to 2.7 V but not the full USB full speed electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 3. Guaranteed by design, not tested in production. 4. RL is the load connected on the USB OTG FS drivers. Note: When VBUS sensing feature is enabled, PA9 should be left at their default state (floating input), not as alternate function.
PAGE 136
Electrical characteristics 6.3.20 STM32F412xE/G 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 71 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 15. Table 71.
PAGE 137
STM32F412xE/G Electrical characteristics Table 71. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit 12-bit resolution Single ADC - - 2 Msps 12-bit resolution Interleave Dual ADC mode - - 3.
PAGE 138
Electrical characteristics STM32F412xE/G Table 73. ADC accuracy at fADC = 30 MHz(1) Symbol ET Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fADC = 30 MHz, RAIN < 10 kΩ, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V, VDDA −VREF < 1.2 V Typ Max(2) ±2 ±5 ±1.5 ±2.5 ±1.5 ±4 ±1 ±2 ±1.5 ±3 Unit LSB 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 2.
PAGE 139
STM32F412xE/G Note: Electrical characteristics ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.
PAGE 140
Electrical characteristics STM32F412xE/G Figure 47. Typical connection diagram using the ADC 9'' 6DPSOH DQG KROG $'& FRQYHUWHU 97 9 5$,1 9$,1 5$'& $,1[ &SDUDVLWLF 97 9 ELW FRQYHUWHU ,/ $ &$'& 06 9 1. Refer to Table 71 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy.
PAGE 141
STM32F412xE/G Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 48 or Figure 49, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 48. Power supply and reference decoupling (VREF+ not connected to VDDA) 670 ) 95() ) Q) 9''$ ) Q) 966$ 95() DL E 1.
PAGE 142
Electrical characteristics STM32F412xE/G Figure 49. Power supply and reference decoupling (VREF+ connected to VDDA) 670 ) 95() 9''$ ) Q) 95() 966$ DL F 1. VREF+ and VREF- inputs are both available on UFBGA100. VREF+ is also available on LQFP100. When VREF+ and VREF- are not available, they are internally connected to VDDA and VSSA. 6.3.21 Temperature sensor characteristics Table 77.
PAGE 143
STM32F412xE/G 6.3.22 Electrical characteristics VBAT monitoring characteristics Table 79. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit KΩ R Resistor bridge for VBAT - 50 - Q Ratio on VBAT measurement - 4 - Error on Q –1 - +1 % ADC sampling time when reading the VBAT 1 mV accuracy 5 - - µs (1) Er TS_vbat(2)(2) 1. Guaranteed by design, not tested in production. 2. Shortest sampling time can be determined in the application by multiple iterations. 6.3.
PAGE 144
Electrical characteristics 6.3.24 STM32F412xE/G DFSDM characteristics Unless otherwise specified, the parameters given in Table 82 for DFSDM are derived from tests performed under the ambient temperature, fAPB2 frequency and VDD supply voltage conditions summarized in Table 15: General operating conditions. • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.
PAGE 145
STM32F412xE/G Electrical characteristics ')6'0B &.,1\ ')6'0B'$7,1\ 63, WLPLQJ 63,&.6(/ Figure 16: DFSDM timing diagram WZO WZK WU WI 63,&.6(/ WVX WK 6,73 WVX WK 6,73 ')6'0B&.287 63,&.6(/ WZO WU WZK WI 63,&.6(/ ')6'0B'$7,1\ WVX ')6'0B'$7,1\ 0DQFKHVWHU WLPLQJ 63, WLPLQJ 63,&.6(/ 63,&.6(/ WK 6,73 WVX WK 6,73 6,73 6,73 5HFRYHUHG FORFN 5HFRYHUHG GDWD 06Y 9 6.3.
PAGE 146
Electrical characteristics STM32F412xE/G Refer to Section 6.3.16: I/O port characteristics for more details on the input/output characteristics. Asynchronous waveforms and timings Figure 50 through Figure 53 represent asynchronous waveforms and Table 83 through Table 90 provide the corresponding timings.
PAGE 147
STM32F412xE/G Electrical characteristics Table 83. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) Symbol Min Max 2THCLK – 1 2 THCLK + 0.5 0 1 2THCLK - 1.5 2THCLK FSMC_NOE high to FSMC_NE high hold time 0 - FSMC_NEx low to FSMC_A valid - 1.5 th(A_NOE) Address hold time after FSMC_NOE high 0 - tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0.
PAGE 148
Electrical characteristics STM32F412xE/G Figure 51. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms WZ 1( )60&B1([ )60&B12( WY 1:(B1( WK 1(B1:( WZ 1:( )60&B1:( WK $B1:( WY $B1( )60&B$> @ $GGUHVV WY %/B1( )60&B1%/> @ WK %/B1:( 1%/ WY 'DWDB1( WK 'DWDB1:( 'DWD )60&B'> @ WY 1$'9B1( )60&B1$'9 WZ 1$'9 )60&B1:$,7 WK 1(B1:$,7 WVX 1:$,7B1( 06Y 9 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 85.
PAGE 149
STM32F412xE/G Electrical characteristics 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 86. Asynchronous non-multiplexed SRAM/PSRAM/NOR write NWAIT timings(1)(2) Symbol Parameter Min Max 8THCLK - 1 8THCLK + 0.5 6THCLK + 0.5 6THCLK + 1 FSMC_NE low time tw(NE) tw(NWE) FSMC_NWE low time tsu(NWAIT_NE) FSMC_NWAIT valid before FSMC_NEx high 6THCLK + 0.5 - th(NE_NWAIT) FSMC_NEx hold time after FSMC_NWAIT invalid - 4THCLK + 1 Unit ns 1. CL = 30 pF. 2.
PAGE 150
Electrical characteristics STM32F412xE/G Table 87. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Symbol tw(NE) tv(NOE_NE) ttw(NOE) th(NE_NOE) tv(A_NE) tv(NADV_NE) tw(NADV) Parameter Min Max 3THCLK – 1 3THCLK + 0.5 2THCLK 2THCLK + 1 THCLK – 1.5 THCLK FSMC_NOE high to FSMC_NE high hold time 0 - FSMC_NEx low to FSMC_A valid - 0.5 FSMC_NEx low to FSMC_NADV low 0 1 THCLK – 0.5 THCLK + 0.
PAGE 151
STM32F412xE/G Electrical characteristics Figure 53. Asynchronous multiplexed PSRAM/NOR write waveforms WZ 1( )60&B1([ )60&B12( WK 1(B1:( WZ 1:( WY 1:(B1( )60&B1:( WK $B1:( WY $B1( )60&B$> @ $GGUHVV WY %/B1( WK %/B1:( )60&B1%/> @ 1%/ WY $B1( )60&B$'> @ WY 'DWDB1$'9 $GGUHVV W Y 1$'9B1( WK 'DWDB1:( 'DWD WK $'B1$'9 WZ 1$'9 )60&B1$'9 )60&B1:$,7 WK 1(B1:$,7 WVX 1:$,7B1( DocID028087 Rev 4 06Y 9 151/193 161 Downloaded from Arrow.com.
PAGE 152
Electrical characteristics STM32F412xE/G Table 89. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Symbol Min Max 4THCLK - 1 4THCLK+0.5 THCLK THCLK + 1 2THCLK - 1 2THCLK + 0.5 THCLK - 1.5 - FSMC_NEx low to FSMC_A valid - 2 FSMC_NEx low to FSMC_NADV low 0 1 THCLK – 0.5 THCLK+ 0.5 THCLK - THCLK- 1.5 - THCLK - FSMC_NEx low to FSMC_BL valid - 1.5 tv(Data_NADV) FSMC_NADV high to Data valid - THCLK + 2 th(Data_NWE) Data hold time after FSMC_NWE high THCLK + 0.
PAGE 153
STM32F412xE/G Electrical characteristics In all timing tables, the THCLK is the HCLK clock period (with maximum FSMC_CLK = 90 MHz). Figure 54. Synchronous multiplexed NOR/PSRAM read timings WZ &/. %867851 WZ &/. )60&B&/. 'DWD ODWHQF\ WG &/./ 1([/ )60&B1([ WG &/./ 1$'9/ WG &/.+ 1([+ WG &/./ 1$'9+ )60&B1$'9 WG &/.+ $,9 WG &/./ $9 )60&B$> @ WG &/./ 12(/ WG &/.+ 12(+ )60&B12( WG &/./ $',9 WG &/./ $'9 )60&B$'> @ WK &/.+ $'9 WVX $'9 &/.+ WVX $'9 &/.+ $'> @ ' WVX 1:$,79 &/.
PAGE 154
Electrical characteristics STM32F412xE/G Table 91. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol tw(CLK) Parameter FSMC_CLK period 2THCLK - 0.5 - - 1 THCLK + 0.5 - FSMC_CLK low to FSMC_NEx low (x=0..
PAGE 155
STM32F412xE/G Electrical characteristics Figure 55. Synchronous multiplexed PSRAM write timings WZ &/. %867851 WZ &/. )60&B&/. 'DWD ODWHQF\ WG &/./ 1([/ WG &/.+ 1([+ )60&B1([ WG &/./ 1$'9/ WG &/./ 1$'9+ )60&B1$'9 WG &/.+ $,9 WG &/./ $9 )60&B$> @ WG &/.+ 1:(+ WG &/./ 1:(/ )60&B1:( WG &/./ $',9 WG &/./ $'9 )60&B$'> @ WG &/./ 'DWD WG &/./ 'DWD $'> @ ' ' )60&B1:$,7 :$,7&)* E :$,732/ E WVX 1:$,79 &/.+ WK &/.+ 1:$,79 WG &/.
PAGE 156
Electrical characteristics STM32F412xE/G Table 92. Synchronous multiplexed PSRAM write timings(1)(2) Symbol Parameter FSMC_CLK period, VDD range= 2.7 to 3.6 V 2THCLK - 0.5 - td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x= 0...2) - 1 td(CLKH-NExH) FSMC_CLK high to FSMC_NEx high (x= 0…2) THCLK + 0.5 - td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1 td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 0 - - 2 THCLK - - 1.5 THCLK + 0.
PAGE 157
STM32F412xE/G Electrical characteristics Figure 56. Synchronous non-multiplexed NOR/PSRAM read timings WZ &/. WZ &/. )60&B&/. WG &/./ 1([/ WG &/.+ 1([+ 'DWD ODWHQF\ )60&B1([ WG &/./ 1$'9/ WG &/./ 1$'9+ )60&B1$'9 WG &/./ $9 WG &/.+ $,9 )60&B$> @ WG &/.+ 12(+ WG &/./ 12(/ )60&B12( WVX '9 &/.+ WK &/.+ '9 WVX '9 &/.+ ' )60&B'> @ WVX 1:$,79 &/.+ )60&B1:$,7 :$,7&)* E :$,732/ E ' WK &/.+ 1:$,79 WVX 1:$,79 &/.+ )60&B1:$,7 :$,7&)* E :$,732/ E WVX 1:$,79 &/.+ WK &/.
PAGE 158
Electrical characteristics STM32F412xE/G 1. CL = 30 pF. 2. Based on characterization, not tested in production. Figure 57. Synchronous non-multiplexed PSRAM write timings WZ &/. WZ &/. )60&B&/. WG &/./ 1([/ WG &/.+ 1([+ 'DWD ODWHQF\ )60&B1([ WG &/./ 1$'9/ WG &/./ 1$'9+ )60&B1$'9 WG &/./ $9 WG &/.+ $,9 )60&B$> @ WG &/./ 1:(/ WG &/.+ 1:(+ )60&B1:( WG &/./ 'DWD )60&B'> @ )60&B1:$,7 :$,7&)* E :$,732/ E WG &/./ 'DWD ' WVX 1:$,79 &/.+ ' WG &/.+ 1%/+ WK &/.
PAGE 159
STM32F412xE/G Electrical characteristics Table 94. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol Min Max 2THCLK – 0.5 - - 1 THCLK + 0.5 - td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1 td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 0 - - 2 THCLK - - 1.5 THCLK + 0.5 - tw(CLK) td(CLKL-NExL) Parameter FSMC_CLK period FSMC_CLK low to FSMC_NEx low (x=0..
PAGE 160
Electrical characteristics STM32F412xE/G Figure 58. SDIO high-speed mode TF TR T# T7 #+( T7 #+, #+ T/6 T/( $ #-$ OUTPUT T)35 T)( $ #-$ INPUT AI Figure 59. SD default mode #+ T/6$ T/($ $ #-$ OUTPUT AI Table 95. Dynamic characteristics: SD / MMC characteristics(1)(2) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode - 0 - 50 MHz - SDIO_CK/fPCLK2 frequency ratio - - - 8/3 - tW(CKL) Clock low time fpp =50MHz 9.5 10.
PAGE 161
STM32F412xE/G Electrical characteristics Table 95. Dynamic characteristics: SD / MMC characteristics(1)(2) (continued) Symbol Parameter Conditions Min Typ Max Unit CMD, D inputs (referenced to CK) in SD default mode tISUD Input setup time SD fpp =25MHz 2.5 - - tIHD Input hold time SD fpp =25MHz 2.5 - - ns CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD fpp =25 MHz - 1.5 2 tOHD Output hold default time SD fpp =25 MHz 0.5 - - ns 1.
PAGE 162
Package information 7 STM32F412xE/G Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 WLCSP64 package information Figure 60. WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.
PAGE 163
STM32F412xE/G Package information Table 98. WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.170 - - 0.0067 - A2 - 0.380 - - 0.0150 - - 0.025 - - 0.0010 - b(3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 3.588 3.623 3.658 0.1413 0.1426 0.1440 E 3.616 3.651 3.686 0.1424 0.1437 0.1451 e - 0.400 - - 0.
PAGE 164
Package information STM32F412xE/G Table 99. WLCSP64 recommended PCB design rules (0.4 mm pitch) (continued) Dimension Recommended values Dsm 0.290 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.250 mm Stencil thickness 0.100 mm Device marking for WLCSP64 The following figure gives an example of topside marking and pin 1 position identifier location. Figure 62.
PAGE 165
STM32F412xE/G 7.2 Package information UFQFPN48 package information Figure 63. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline 3LQ LGHQWLILHU ODVHU PDUNLQJ DUHD ' $ ( ( 7 GGG $ 6HDWLQJ SODQH E H 'HWDLO < ' ([SRVHG SDG DUHD < ' / & [ SLQ FRUQHU 5 W\S 'HWDLO = ( = $ % B0(B9 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3.
PAGE 166
Package information STM32F412xE/G Table 100. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 T - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - ddd - - 0.080 - - 0.0031 1.
PAGE 167
STM32F412xE/G Package information Device marking for UFQFPN48 The following figure gives an example of topside marking and pin 1 position identifier location. Figure 65. UFQFPN48 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ 670 ) &*8 'DWH FRGH < :: 3LQ LQGHQWLILHU 5HYLVLRQ FRGH 5 06Y 9 1.
PAGE 168
Package information 7.3 STM32F412xE/G LQFP64 package information Figure 66. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline PP *$8*( 3/$1( F $ $ $ 6($7,1* 3/$1( & $ FFF & ' ' ' . / / 3,1 ,'(17,),&$7,21 ( ( ( E H :B0(B9 1. Drawing is not to scale. 168/193 Downloaded from Arrow.com.
PAGE 169
STM32F412xE/G Package information Table 101. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.
PAGE 170
Package information STM32F412xE/G Figure 67. LQFP64 recommended footprint AI C 1. Dimensions are in millimeters. Device marking for LQFP64 The following figure gives an example of topside marking and pin 1 position identifier location. Figure 68. LQFP64 marking example (package top view) 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ 5 670 ) 5*7 'DWH FRGH < :: 3LQ LQGHQWLILHU 06Y 9 1.
PAGE 171
STM32F412xE/G 7.4 Package information LQFP100 package information Figure 69. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline MM C ! ! ! 3%!4).' 0,!.% # '!5'% 0,!.% $ ! + CCC # , $ , $ 0). )$%.4)&)#!4)/. % % % B E ,?-%?6 1. Drawing is not to scale. Dimensions are in millimeters. Table 102.
PAGE 172
Package information STM32F412xE/G Table 102. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0.0° 3.5° 7.0° 0.0° 3.5° 7.
PAGE 173
STM32F412xE/G Package information Device marking for LQFP100 The following figure gives an example of topside marking and pin 1 position identifier location. Figure 71. LQFP100 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ (6 ) 9*7 5 5HYLVLRQ FRGH 'DWH FRGH < :: 3LQ LQGHQWLILHU 06Y 9 1.
PAGE 174
Package information 7.5 STM32F412xE/G LQFP144 package information Figure 72. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline C ! ! ! 3%!4).' 0,!.% # MM CCC # $ , $ + ! '!5'% 0,!.% , $ % % % B 0). )$%.4)&)#!4)/. E !?-%?6 1. Drawing is not to scale. 174/193 Downloaded from Arrow.com.
PAGE 175
STM32F412xE/G Package information Table 103. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.8740 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.
PAGE 176
Package information STM32F412xE/G Figure 73. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint DL H 1. Dimensions are expressed in millimeters. 176/193 Downloaded from Arrow.com.
PAGE 177
STM32F412xE/G Package information Device marking for LQFP144 The following figure gives an example of topside marking and pin 1 position identifier location. Figure 74. LQFP144 marking example (package top view) 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ 5 (6 ) =*7 'DWH FRGH < :: 3LQ LGHQWLILHU 06Y 9 1.
PAGE 178
Package information 7.6 STM32F412xE/G UFBGA100 package information Figure 75. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline = 6HDWLQJ SODQH GGG = $ $ $ $ $ ( H $ EDOO $ EDOO LGHQWLILHU LQGH[ DUHD ) ; ( $ ) ' ' H < 0 %27720 9,(: E EDOOV HHH 0 = < ; III 0 = 723 9,(: $ & B0(B9 1. Drawing is not to scale. Table 104. UFBGA100 - 100-pin, 7 x 7 mm, 0.
PAGE 179
STM32F412xE/G Package information Table 104. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 76. UFBGA100 - 100-pin, 7 x 7 mm, 0.
PAGE 180
Package information STM32F412xE/G Device marking for UFBGA100 The following figure gives an example of topside marking and ball 1 position identifier location. Figure 77. UFBGA100 marking example (package top view) WƌŽĚƵĐƚ ŝĚĞŶƚŝĨŝĐĂƚŝŽŶ;ϭͿ 670 ) 9*+ ĂƚĞ ĐŽĚĞ с ǇĞĂƌ н ǁĞĞŬ < :: Ăůů ϭ ŝĚĞŶƚŝĨŝĐĂƚŝŽŶ ĚĚŝƚŝŽŶĂů ŝŶĨŽƌŵĂƚŝŽŶ = 06Y 9 1.
PAGE 181
STM32F412xE/G 7.7 Package information UFBGA144 package information Figure 78. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package outline & 6HDWLQJ SODQH GGG = $ $ $ $ $ ( H $ EDOO $ EDOO LGHQWLILHU LQGH[ DUHD ) $ ( $ ) ' ' H % 0 %27720 9,(: E EDOOV HHH 0 & $ % III 0 & 723 9,(: $
PAGE 182
Package information STM32F412xE/G Table 106. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. F 0.550 0.600 0.650 0.0177 0.0197 0.0217 ddd - - 0.080 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 79. UFBGA144 - 144-pin, 10 x 10 mm, 0.
PAGE 183
STM32F412xE/G Package information Device marking for UFBGA144 The following figure gives an example of topside marking and ball A1 position identifier location. Figure 80. UFBGA144 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ 670 ) =*- $GGLWLRQDO LQIRUPDWLRQ = 'DWH FRGH < :: %DOO $ LQGHQWLILHU 06Y 9 1.
PAGE 184
Package information 7.8 STM32F412xE/G Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 15: General operating conditions on page 76. The maximum chip-junction temperature, TJ max.
PAGE 185
STM32F412xE/G 8 Part numbering Part numbering Table 109.
PAGE 186
Recommendations when using the internal reset OFF Appendix A STM32F412xE/G Recommendations when using the internal reset OFF When the internal reset is OFF, the following integrated features are no longer supported: 186/193 Downloaded from Arrow.com. • The integrated power-on-reset (POR)/power-down reset (PDR) circuitry is disabled. • The brownout reset (BOR) circuitry must be disabled. By default BOR is OFF. • The embedded programmable voltage detector (PVD) is disabled.
PAGE 187
STM32F412xE/G Appendix B B.1 Application block diagrams Application block diagrams USB OTG full speed (FS) interface solutions Figure 81. USB controller configured as peripheral-only and used in Full speed mode 9''86% 9'' 9 WR 9''86% 9ROWDJH UHJXODWRU 9%86 '0 3$ 26&B,1 '3 3$ 26&B287 966 86% 6WG % FRQQHFWRU 670 ) [[ SLQV SDFNDJHV 06Y 9 1. External voltage regulator only needed when building a VBUS powered device. Figure 82.
PAGE 188
Application block diagrams STM32F412xE/G Figure 83. USB peripheral-only Full speed mode, VBUS detection using GPIO 9 9'' 9 9''86% *3,2 9%86 '0 3$ 26&B,1 '3 3$ 26&B287 966 86% 6WG % FRQQHFWRU 670 ) [[ SLQV SDFNDJHV 06Y 9 1. External voltage regulator only needed when building a VBUS powered device. Figure 84.
PAGE 189
STM32F412xE/G Application block diagrams Figure 85. USB controller configured in dual mode and used in full speed mode 9'' 9 WR 9'' 9ROWDJH UHJXODWRU 9'' (1 2YHUFXUUHQW *3,2 ,54 &XUUHQW OLPLWHU SRZHU VZLWFK 9 9%86 3$ '0 3$ 26&B,1 26&B287 '3 3$ ,' 3$ 966 86% PLFUR $% FRQQHFWRU 670 ) [[ *3,2 06Y 9 1. External voltage regulator only needed when building a VBUS powered device. 2.
PAGE 190
Application block diagrams B.3 STM32F412xE/G Display application example Figure 87. Display application example 670 ) SLQ SDFNDJH 7,0 BFK N %227 1:( $ 1( 12( )60& -7$* 6:',2 6:&/. 6:2 3$ 3$ 3% ' ' ' ' ' ' ' ' *3,2 %DFNOLJKW FRQWURO 7( 7HDULQJ 3& 3& 3& 3& :5 '& &6 5' 3& 3% 3& 3& 3& 3$ 3$ 3$ 3$ 'LVSOD\ 0RGXOH >' ' @ *3,2 ,QWHUUXSW 3% 3% 6&/ , & 6'$ 7RXFK 6FUHHQ &RQWUROOHU 06Y 9 Note: 190/193 Downloaded from Arrow.com.
PAGE 191
STM32F412xE/G Revision history Revision history Table 110. Document revision history Date Revision 10-Nov-2015 1 Initial release. 2 Added – Table 3: Embedded bootloader interfaces – Figure 3: Compatible board design for LQFP144 package – Figure 62: WLCSP64 marking example (package top view) – Figure 77: UFBGA100 marking example (package top view) Updated – Section 3.17: Power supply schemes – Section 3.23: Timers and watchdogs – Section 3.
PAGE 192
Revision history STM32F412xE/G Table 110. Document revision history Date 25-Mar-2016 27-May-2016 192/193 Downloaded from Arrow.com. Revision Changes 3 Added: – Figure 82: USB peripheral-only Full speed mode with direct connection for VBUS sense – Figure 83: USB peripheral-only Full speed mode, VBUS detection using GPIO Updated: – Figure 15: STM32F412xE/G LQFP144 pinout – Section 6.3.
PAGE 193
STM32F412xE/G IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.