Datasheet
Pinouts and pin description STM32F411xC STM32F411xE
46/149 DocID026289 Rev 6
43 59 D4 93 B4 PB7 I/O FT -
TIM4_CH2,
I2C1_SDA,
USART1_RX,
SDIO_D0,
EVENTOUT
-
44 60 A5 94 A4 BOOT0 I B - - VPP
45 61 B5 95 A3 PB8 I/O FT -
TIM4_CH3,
TIM10_CH1,
I2C1_SCL,
SPI5_MOSI/I2S5_SD,
I2C3_SDA, SDIO_D4,
EVENTOUT
-
46 62 C5 96 B3 PB9 I/O FT -
TIM4_CH4,
TIM11_CH1,
I2C1_SDA,
SPI2_NSS/I2S2_WS,
I2C2_SDA, SDIO_D5,
EVENTOUT
-
- - - 97 C3 PE0 I/O FT -
TIM4_ETR,
EVENTOUT
-
- - - 98 A2 PE1 I/O FT - EVENTOUT -
47 63 A6 99 - VSS S - - - -
- - B6 - H3 PDR_ON I FT - - -
48 64 A7 100 - VDD S - - - -
1. Function availability depends on the chosen device.
2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These I/Os must not be used as a current source (e.g. to drive an LED).
3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after
reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC
register description sections in the STM32F411xx reference manual.
4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
5. If the device is delivered in an UFBGA100 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset ON mode),
then PA0 is used as an internal Reset (active low)
Table 8. STM32F411xC/xE pin definitions (continued)
Pin number
Pin name
(function after
reset)
(1)
Pin type
I/O structure
Notes
Alternate functions Additional functions
UFQFPN48
LQFP64
WLCSP49
LQFP100
UFBGA100
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