Datasheet

Functional overview STM32F411xC STM32F411xE
20/149 DocID026289 Rev 6
buses is 100 MHz while the maximum frequency of the high-speed APB domains is
100 MHz. The maximum allowed frequency of the low-speed APB domain is 50 MHz.
The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class
performance. In this case, the I
2
S master clock can generate all standard sampling
frequencies from 8 kHz to 192 kHz.
3.13 Boot modes
At startup, boot pins are used to select one out of three boot options:
• Boot from user Flash
• Boot from system memory
• Boot from embedded SRAM
The bootloader is located in system memory. It is used to reprogram the Flash memory by
using USART1(PA9/10), USART2(PD5/6), USB OTG FS in device mode (PA11/12) through
DFU (device firmware upgrade), I2C1(PB6/7), I2C2(PB10/3), I2C3(PA8/PB4),
SPI1(PA4/5/6/7), SPI2(PB12/13/14/15) or SPI3(PA15, PC10/11/12).
For more detailed information on the bootloader, refer to Application Note: AN2606,
STM32™ microcontroller system memory boot mode.
3.14 Power supply schemes
• VDD = 1.7 to 3.6 V: external power supply for I/Os with the internal supervisor
(POR/PDR) disabled, provided externally through VDD pins. Requires the use of an
external power supply supervisor connected to the VDD and NRST pins.
• V
SSA
, V
DDA
= 1.7 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs
and PLL. V
DDA
and V
SSA
must be connected to V
DD
and V
SS
, respectively, with
decoupling technique.
• V
BAT
= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when V
DD
is not present.
Refer to Figure 17: Power supply scheme for more details.
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