Datasheet

Recommendations when using the internal reset OFF STM32F411xC STM32F411xE
142/149 DocID026289 Rev 6
Appendix A Recommendations when using the internal
reset OFF
When the internal reset is OFF, the following integrated features are no longer supported:
• The integrated power-on-reset (POR)/power-down reset (PDR) circuitry is disabled.
• The brownout reset (BRO) circuitry must be disabled. By default BOR is OFF.
• The embedded programmable voltage detector (PVD) is disabled.
• V
BAT
functionality is no more available and VBAT pin should be connected to V
DD
.
A.1 Operating conditions
Table 87. Limitations depending on the operating power supply range
Operating
power supply
range
ADC
operation
Maximum
Flash memory
access
frequency
with no wait
state
(f
Flashmax
)
Maximum
Flash memory
access
frequency
with no wait
states
(1) (2)
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no
wait state is required.
2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does
not impact the execution speed from Flash memory since the ART accelerator allows to achieve a
performance equivalent to 0 wait state program execution.
I/O operation
Possible
Flash memory
operations
V
DD
= 1.7 to
2.1 V
(3)
3. V
DD
/V
DDA
minimum value of 1.7 V, with the use of an external power supply supervisor (refer to
Section 3.15.1: Internal reset ON).
Conversion
time up to
1.2 Msps
20 MHz
(4)
4. Prefetch is not available. Refer to AN3430 application note for details on how to adjust performance and
power.
100 MHz with
6 wait states
No I/O
compensation
8-bit erase and
program
operations only
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