Datasheet

DocID026289 Rev 6 107/149
STM32F411xC STM32F411xE Electrical characteristics
123
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 60 for the SPI interface are
derived from tests performed under the ambient temperature, f
PCLKx
frequency and V
DD
supply voltage conditions summarized in Table 14, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 60. SPI dynamic characteristics
(1)
Symbol Parameter Conditions Min Typ Max Unit
f
SCK
1/t
c(SCK)
SPI clock frequency
Master full duplex/receiver mode,
2.7 V < V
DD
< 3.6 V
SPI1/4/5
--42
MHz
Master full duplex/receiver mode,
3.0 V < V
DD
< 3.6 V
SPI1/4/5
--
50
Master transmitter mode
1.7 V < V
DD
< 3.6 V
SPI1/4/5
--
50
Master mode
1.7 V < V
DD
< 3.6 V
SPI1/2/3/4/5
--
25
Slave transmitter/full duplex mode
2.7 V < V
DD
< 3.6 V
SPI1/4/5
--
38
(2)
Slave receiver mode,
1.8 V < V
DD
< 3.6 V
SPI1/4/5
--50
Slave mode,
1.8 V < V
DD
< 3.6 V
SPI1/2/3/4/5
--
25
Duty(SCK)
Duty cycle of SPI clock
frequency
Slave mode 30 50 70 %
t
w(SCKH)
t
w(SCKL)
SCK high and low time Master mode, SPI presc = 2 T
PCLK
−1.5
T
PCLK
T
PCLK
+1.5
ns
t
su(NSS)
NSS setup time Slave mode, SPI presc = 2 3T
PCLK
--ns
t
h(NSS)
NSS hold time Slave mode, SPI presc = 2 2T
PCLK
--ns
t
su(MI)
Data input setup time
Master mode 4 - - ns
t
su(SI)
Slave mode 2.5 - - ns
t
h(MI)
Data input hold time
Master mode 7.5 - - ns
t
h(SI)
Slave mode 3.5 - - ns
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