Datasheet

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STM32F411xC STM32F411xE Electrical characteristics
123
6.3.17 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R
PU
(see Table 53).
Unless otherwise specified, the parameters given in Table 56 are derived from tests
performed under the ambient temperature and V
DD
supply voltage conditions summarized
in Table 14. Refer to Table 53: I/O static characteristics for the values of VIH and VIL for
NRST pin.
Figure 32. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
IL(NRST)
max level specified in
Table 56. Otherwise the reset is not taken into account by the device.
Table 56. NRST pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
R
PU
Weak pull-up equivalent
resistor
(1)
V
IN
= V
SS
30 40 50 kΩ
V
F(NRST)
(2)
NRST Input filtered pulse - - 100 ns
V
NF(NRST)
(2)
NRST Input not filtered pulse V
DD
> 2.7 V 300 - - ns
T
NRST_OUT
Generated reset pulse duration
Internal Reset
source
20 - - µs
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum
(~10% order).
2. Guaranteed by design.
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