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This is information on a product in full production.

December 2016 DocID026289 Rev 6 1/149

STM32F411xC STM32F411xE

ARM

Cortex

-M4 32b MCU+FPU, 125 DMIPS, 512KB Flash,

128KB RAM, USB OTG FS, 11 TIMs, 1 ADC, 13 comm. interfaces

Datasheet - production data

Features

• Dynamic Efficiency Line with BAM (Batch

Acquisition Mode)

– 1.7 V to 3.6 V power supply

– - 40°C to 85/105/125 °C temperature range

• Core: ARM

32-bit Cortex

-M4 CPU with

FPU, Adaptive real-time accelerator (ART

Accelerator™) allowing 0-wait state execution

from Flash memory, frequency up to 100 MHz,

memory protection unit,

125 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1),

and DSP instructions

• Memories

– Up to 512 Kbytes of Flash memory

– 128 Kbytes of SRAM

• Clock, reset and supply management

– 1.7 V to 3.6 V application supply and I/Os

– POR, PDR, PVD and BOR

– 4-to-26 MHz crystal oscillator

– Internal 16 MHz factory-trimmed RC

– 32 kHz oscillator for RTC with calibration

– Internal 32 kHz RC with calibration

• Power consumption

– Run: 100 µA/MHz (peripheral off)

– Stop (Flash in Stop mode, fast wakeup

time): 42 µA Typ @ 25C; 65 µA max

@25 °C

– Stop (Flash in Deep power down mode,

slow wakeup time): down to 9 µA @ 25 °C;

28 µA max @25 °C

– Standby: 1.8 µA @25 °C / 1.7 V without

RTC; 11 µA @85 °C @1.7 V

–V

BAT

supply for RTC: 1 µA @25 °C

• 1×12-bit, 2.4 MSPS A/D converter: up to 16

channels

• General-purpose DMA: 16-stream DMA

controllers with FIFOs and burst support

• Up to 11 timers: up to six 16-bit, two 32-bit

timers up to 100 MHz, each with up to four

IC/OC/PWM or pulse counter and quadrature

(incremental) encoder input, two watchdog

timers (independent and window) and a

SysTick timer

• Debug mode

– Serial wire debug (SWD) & JTAG

interfaces

–Cortex



-M4 Embedded Trace Macrocell™

• Up to 81 I/O ports with interrupt capability

– Up to 78 fast I/Os up to 100 MHz

– Up to 77 5 V-tolerant I/Os

• Up to 13 communication interfaces

– Up to 3 x I

C interfaces (SMBus/PMBus)

– Up to 3 USARTs (2 x 12.5 Mbit/s,

1 x 6.25 Mbit/s), ISO 7816 interface, LIN,

IrDA, modem control)

– Up to 5 SPI/I2Ss (up to 50 Mbit/s, SPI or

I2S audio protocol), SPI2 and SPI3 with

muxed full-duplex I

S to achieve audio

class accuracy via internal audio PLL or

external clock

– SDIO interface (SD/MMC/eMMC)

– Advanced connectivity: USB 2.0 full-speed

device/host/OTG controller with on-chip

PHY

• CRC calculation unit

• 96-bit unique ID

• RTC: subsecond accuracy, hardware calendar

• All packages (WLCSP49, LQFP64/100,

UFQFPN48, UFBGA100) are ECOPACK

Table 1. Device summary

Reference Part number

STM32F411xC

STM32F411CC, STM32F411RC,

STM32F411VC

STM32F411xE

STM32F411CE, STM32F411RE,

STM32F411VE

WLCSP49

)%*$

UFQFPN48

(7 × 7 mm)

UFBGA100

(7 × 7 mm)

(2.999x3.185 mm)

LQFP100

(14 × 14mm)

LQFP64

(10x10 mm)

www.st.com

Downloaded from Arrow.com.

Summary of content (149 pages)

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STM32F411xC STM32F411xE ARM® Cortex®-M4 32b MCU+FPU, 125 DMIPS, 512KB Flash, 128KB RAM, USB OTG FS, 11 TIMs, 1 ADC, 13 comm. interfaces Datasheet - production data Features • Dynamic Efficiency Line with BAM (Batch Acquisition Mode) – 1.7 V to 3.
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Contents STM32F411xC STM32F411xE Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 3 Compatibility with STM32F4 series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.
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STM32F411xC STM32F411xE Contents 3.20.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.20.3 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.20.4 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.20.5 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.
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Contents 7 STM32F411xC STM32F411xE 6.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 66 6.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.7 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . .
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STM32F411xC STM32F411xE Contents B.1 USB OTG Full Speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . 143 B.2 Sensor Hub application example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 B.3 Batch Acquisition Mode (BAM) example . . . . . . . . . . . . . . . . . . . . . . . . . 146 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 DocID026289 Rev 6 5/149 5 Downloaded from Arrow.com.
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List of tables STM32F411xC STM32F411xE List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. 6/149 Downloaded from Arrow.com. Device summary . .
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STM32F411xC STM32F411xE Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88.
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List of figures STM32F411xC STM32F411xE List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42.
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STM32F411xC STM32F411xE Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. List of figures chip scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 WLCSP49 - 49-ball, 2.999 x 3.185 mm, 0.4 mm pitch wafer level chip scale recommended footprint . . . . . . . . . . . . . . . . . . .
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Introduction 1 STM32F411xC STM32F411xE Introduction This datasheet provides the description of the STM32F411xC/xE line of microcontrollers. The STM32F411xC/xE datasheet should be read in conjunction with RM0383 reference manual which is available from the STMicroelectronics website www.st.com. It includes all information concerning Flash memory programming. For information on the Cortex®-M4 core, please refer to the Cortex®-M4 programming manual (PM0214) available from www.st.com.
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STM32F411xC STM32F411xE 2 Description Description The STM32F411XC/XE devices are based on the high-performance ARM® Cortex® -M4 32bit RISC core operating at a frequency of up to 100 MHz. The Cortex®-M4 core features a Floating point unit (FPU) single precision which supports all ARM single-precision dataprocessing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.
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Description STM32F411xC STM32F411xE Table 2. STM32F411xC/xE features and peripheral counts Peripherals Flash memory in Kbytes SRAM in Kbytes Timers STM32F411xC STM32F411xE 256 512 System 128 Generalpurpose 7 Advancedcontrol 1 SPI/ I2S Communication interfaces 5/5 (2 full duplex) I2C 3 USART 3 SDIO 1 USB OTG FS 1 GPIOs 12-bit ADC Number of channels 36 50 81 10 16 12/149 Downloaded from Arrow.com.
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STM32F411xC STM32F411xE 2.1 Description Compatibility with STM32F4 series The STM32F411xC/xE are fully software and feature compatible with the STM32F4 series (STM32F42x, STM32F401, STM32F43x, STM32F41x, STM32F405 and STM32F407) The STM32F411xC/xE can be used as drop-in replacement of the other STM32F4 products but some slight changes have to be done on the PCB board. Figure 1.
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Description STM32F411xC STM32F411xE Figure 2. Compatible board design for LQFP64 package 670 ) [[ 670 ) [[ 670 ) [[ 670 ) [[ 670 ) [[ 670 ) [[ 670 ) [[ 9'' 9&$3B 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 9'' 966 3% QRW DYDLODEOH DQ\PRUH 5HSODFHG E\ 9&$3B 9'' 966 3$ 3$ 3$ 3$ 3$ 966 3$ 3& 3& 3& 3& 3% 3% 3% 3% 9'' 3% 3% 9&$3B 966 9'' 3% 3% 3% 9&$3B
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STM32F411xC STM32F411xE Description Figure 3. STM32F411xC/xE block diagram -7$* 6: (70 038 19,& ' %86 $50 &RUWH[ 0 0+] , %86 $+% EXV PDWUL[ 6 0 6 %86 6WUHDPV '0$ .% 65$0 $+% 0+] ),)2 86% 27* )6 $+% 0+] 6WUHDPV '0$ .% )ODVK 3RZHU PDQDJPW 9'' ),)2 ),)2 )38 3+< 75$&(&/. 75$&('> @ $&&(/ &$&+( 1-7567 -7', -7&. 6:&/.
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Functional overview STM32F411xC STM32F411xE 3 Functional overview 3.1 ARM® Cortex®-M4 with FPU core with embedded Flash and SRAM The ARM® Cortex®-M4 with FPU processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
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STM32F411xC STM32F411xE 3.4 Functional overview Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.
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Functional overview 3.8 STM32F411xC STM32F411xE Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves (Flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. Figure 4. Multi-AHB matrix 6 '0$B0(0 '0$B0(0 '0$B3, 6 EXV 6 6 6 '0$B3 *3 '0$ *3 '0$ 6 0 ,&2'( 0 '&2'( 0 $&&(/ 6 ' EXV , EXV $50 &RUWH[ 0 )ODVK N% 65$0 .
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STM32F411xC STM32F411xE Functional overview The DMA can be used with the main peripherals: 3.10 • SPI and I2S • I2C • USART • General-purpose, basic and advanced-control timers TIMx • SD/SDIO/MMC/eMMC host interface • ADC Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 62 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M4 with FPU.
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Functional overview STM32F411xC STM32F411xE buses is 100 MHz while the maximum frequency of the high-speed APB domains is 100 MHz. The maximum allowed frequency of the low-speed APB domain is 50 MHz. The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class performance. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. 3.
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STM32F411xC STM32F411xE Functional overview 3.15 Power supply supervisor 3.15.1 Internal reset ON This feature is available for VDD operating voltage range 1.8 V to 3.6 V. The internal power supply supervisor is enabled by holding PDR_ON high. The devices have an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR is always active, and ensures proper operation starting from 1.8 V. After the 1.
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Functional overview STM32F411xC STM32F411xE A comprehensive set of power-saving mode allows to design low-power applications. When the internal reset is OFF, the following integrated features are no longer supported: 3.16 • The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled. • The brownout reset (BOR) circuitry must be disabled. • The embedded programmable voltage detector (PVD) is disabled.
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STM32F411xC STM32F411xE Functional overview When the regulator is OFF, there is no more internal monitoring on V12. An external power supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain. In regulator OFF mode, the following features are no more supported: • PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power domain which is not reset by the NRST pin.
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Functional overview STM32F411xC STM32F411xE Figure 7. Startup in regulator OFF: slow VDD slope power-down reset risen after VCAP_1/VCAP_2 stabilization 9'' 3'5 9 9 0LQ 9 9&$3B 9&$3B WLPH 1567 WLPH 06Y 9 1. This figure is valid whatever the internal reset mode (ON or OFF). Figure 8. Startup in regulator OFF mode: fast VDD slope power-down reset risen before VCAP_1/VCAP_2 stabilization 9'' 3'5 9 9&$3B 9&$3B 9 0LQ 9 1567 WLPH 3$ DVVHUWHG H[WHUQDOO\ WLPH 1.
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STM32F411xC STM32F411xE 3.16.3 Functional overview Regulator ON/OFF and internal power supply supervisor availability Table 3.
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Functional overview STM32F411xC STM32F411xE The RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or from the VBAT pin. 3.18 Low-power modes The devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
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STM32F411xC STM32F411xE 3.20 Functional overview Timers and watchdogs The devices embed one advanced-control timer, seven general-purpose timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 4 compares the features of the advanced-control and general-purpose timers. Table 4.
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Functional overview STM32F411xC STM32F411xE If configured as standard 16-bit timers, it has the same features as the general-purpose TIMx timers. If configured as a 16-bit PWM generator, it has full modulation capability (0100%). The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. TIM1 supports independent DMA request generation. 3.20.
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STM32F411xC STM32F411xE 3.20.5 Functional overview SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: 3.21 • A 24-bit downcounter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0 • Programmable clock source. Inter-integrated circuit interface (I2C) Up to three I2C bus interfaces can operate in multimaster and slave modes.
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Functional overview STM32F411xC STM32F411xE Table 6. USART feature comparison Max. baud Max. baud USART Standard Modem SPI Smartcard rate in Mbit/s rate in Mbit/s APB LIN irDA name features (RTS/CTS) master (ISO 7816) (oversampling (oversampling mapping by 16) by 8) USART1 X X X X X X 6.25 12.5 APB2 (max. 100 MHz) USART2 X X X X X X 3.12 6.25 APB1 (max. 50 MHz) USART6 X N.A X X X X 6.25 12.5 APB2 (max. 100 MHz) 3.
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STM32F411xC STM32F411xE Functional overview In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S flow with an external PLL (or Codec output). 3.26 Secure digital input/output interface (SDIO) An SD/SDIO/MMC/eMMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
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Functional overview 3.29 STM32F411xC STM32F411xE Analog-to-digital converter (ADC) One 12-bit analog-to-digital converter is embedded and shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels.
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STM32F411xC STM32F411xE 4 Pinouts and pin description Pinouts and pin description Figure 9. STM32F411xC/xE WLCSP49 pinout $ 9'' 966 %227 3% 3% 3$ 3$ % 9%$7 3'5 B21 3% 3% 3$ 9'' 966 3% 3% 3$ 3$ 3$ 3% 966 3$ 3$ & 3& 3& 26& B,1 26& B287 ' 3+ 3+ 3& 26&B,1 26&B287 ( 1567 966$ 95() 3$ 3$ 3% 3% 3% ) 9''$ 95() 3$ 3$ 3$ 3$ 9'' 3% * 3$ 3$ 3% 3% 3% 9&$3 3% 06 9 1.
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Pinouts and pin description STM32F411xC STM32F411xE 3% 3% 3% 3% 3$ 3$ 3% 3% %227 966 9%$7 3% 9'' Figure 10.
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STM32F411xC STM32F411xE Pinouts and pin description 9%$7 3& 3& 26& B,1 3% 3% %227 3% 3% 3% 3% 3% 3' 3& 3& 3& 3$ 3$ /4)3 9'' 966 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 3$ 966 9'' 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3% 9&$3B 966 9'' 3& 26& B287 3+ 26&B,
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Pinouts and pin description STM32F411xC STM32F411xE 6$$ 633 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 12.
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STM32F411xC STM32F411xE Pinouts and pin description Figure 13.
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Pinouts and pin description STM32F411xC STM32F411xE Table 7. Legend/abbreviations used in the pinout table Name Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name Pin name Pin type I/O structure Notes S Supply pin I Input only pin I/O Input/ output pin FT 5 V tolerant I/O TC Standard 3.
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STM32F411xC STM32F411xE Pinouts and pin description Table 8.
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Pinouts and pin description STM32F411xC STM32F411xE Table 8.
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STM32F411xC STM32F411xE Pinouts and pin description Table 8.
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Pinouts and pin description STM32F411xC STM32F411xE Table 8.
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STM32F411xC STM32F411xE Pinouts and pin description Table 8.
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Pinouts and pin description STM32F411xC STM32F411xE Table 8.
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STM32F411xC STM32F411xE Pinouts and pin description Table 8.
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Pinouts and pin description STM32F411xC STM32F411xE Table 8.
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/149 Downloaded from Arrow.com. - - PH1 SYS_AF AF00 PH0 Port Port H - - TIM1/TIM2 AF01 - - TIM3/ TIM4/ TIM5 AF02 - - TIM9/ TIM10/ TIM11 AF03 - - I2C1/I2C2/ I2C3 AF04 - - - - SPI3/I2S3/ USART1/ USART2 SPI2/I2S2/ SPI3/ I2S3/SPI4/ I2S4/SPI5/ I2S5 SPI1/I2S1S PI2/ I2S2/SPI3/ I2S3 - AF07 AF06 AF05 - - USART6 AF08 Table 9.
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STM32F411xC STM32F411xE 5 Memory mapping Memory mapping The memory map is shown in Figure 14. Figure 14. Memory map 5HVHUYHG [( [)))) )))) &RUWH[ 0 LQWHUQDO [( [( ) )))) SHULSKHUDOV ['))) )))) 5HVHUYHG [ [ )))) $+% 5HVHUYHG [)))) )))) [( ['))) )))) 0E\WH EORFN &RUWH[ 0 V LQWHUQDO SHULSKHUDOV [ [ [ ))) )))) [ )) $+% 0E\WH EORFN 1RW XVHG [& [%))) )))) 5HVHUYHG [ [ & [
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Memory mapping STM32F411xC STM32F411xE Table 10.
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STM32F411xC STM32F411xE Memory mapping Table 10.
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Memory mapping STM32F411xC STM32F411xE Table 10. STM32F411xC/xE register boundary addresses (continued) Bus APB1 56/149 Downloaded from Arrow.com.
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STM32F411xC STM32F411xE Electrical characteristics 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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Electrical characteristics 6.1.5 STM32F411xC STM32F411xE Pin input voltage The input voltage measurement on a pin of the device is described in Figure 16. Figure 16. Input voltage measurement -#5 PIN 6). -3 6 58/149 Downloaded from Arrow.com.
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STM32F411xC STM32F411xE 6.1.6 Electrical characteristics Power supply scheme Figure 17. Power supply scheme 9%$7 9%$7 WR 9 *3,2V ,1 9&$3B 9&$3B 9'' 966 î Q) î ) /HYHO VKLIWHU 287 î ) RU î ) 9'' %DFNXS FLUFXLWU\ 26& . 57& :DNHXS ORJLF %DFNXS UHJLVWHUV 3RZHU VZLWFK ,2 /RJLF .HUQHO ORJLF &38 GLJLWDO 5$0 9ROWDJH UHJXODWRU )ODVK PHPRU\ %<3$66B5(* 3'5B21 9'' 9''$ 95() Q) ) 5HVHW FRQWUROOHU Q) ) 95()
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Electrical characteristics 6.1.7 STM32F411xC STM32F411xE Current consumption measurement Figure 18. Current consumption measurement scheme ,''B9%$7 9%$7 ,'' 9'' 9''$ DL 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics, Table 12: Current characteristics, and Table 13: Thermal characteristics may cause permanent damage to the device.
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STM32F411xC STM32F411xE Electrical characteristics Table 12. Current characteristics Symbol Ratings Max.
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Electrical characteristics STM32F411xC STM32F411xE 6.3 Operating conditions 6.3.1 General operating conditions Table 14.
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STM32F411xC STM32F411xE Electrical characteristics Table 14.
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Electrical characteristics STM32F411xC STM32F411xE Table 15. Features depending on the operating power supply range (continued) Operating power supply range ADC operation Maximum Flash memory access frequency with no wait states (fFlashmax) VDD = 2.4 to 2.7 V Conversion time up to 2.4 Msps 24 MHz VDD = 2.7 to 3.6 V(6) Conversion time up to 2.
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STM32F411xC STM32F411xE Electrical characteristics Table 16. VCAP_1/VCAP_2 operating conditions(1) Symbol Parameter Conditions CEXT Capacitance of external capacitor with a single VCAP pin available 4.7 µF ESR ESR of external capacitor with a single VCAP pin available <1Ω 1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be replaced by two 100 nF decoupling capacitors. 6.3.
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Electrical characteristics 6.3.5 STM32F411xC STM32F411xE Embedded reset and power control block characteristics The parameters given in Table 19 are derived from tests performed under ambient temperature and VDD supply voltage @ 3.3V. Table 19. Embedded reset and power control block characteristics Symbol VPVD Parameter Conditions Programmable voltage detector level selection VPVDhyst(2) PVD hysteresis VPOR/PDR Downloaded from Arrow.com. Max PLS[2:0]=000 (rising edge) 2.09 2.14 2.
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STM32F411xC STM32F411xE Electrical characteristics Table 19. Embedded reset and power control block characteristics (continued) Symbol IRUSH(2) ERUSH (2) Parameter Conditions Min Typ Max Unit In-Rush current on voltage regulator poweron (POR or wakeup from Standby) - 160 200 mA In-Rush energy on voltage regulator power- VDD = 1.7 V, TA = 125 °C, on (POR or wakeup from IRUSH = 171 mA for 31 µs Standby) - - 5.4 µC 1.
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Electrical characteristics STM32F411xC STM32F411xE Table 20. Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 1.7 V Max(1) Typ Symbol Parameter Conditions fHCLK (MHz) TA= 25 °C TA= 25 °C TA= 85 °C TA= 105 °C TA= 125 °C 21.4 23.0 23.6 24.0 25.0 84 17.2 18.9(5) 19.1 19.2 20.2 64 11.9 12.9 13.2 13.7 14.6 50 9.4 10.1 10.4 11.0 11.9 20 4.3 4.8 5.0 5.6 6.5 16 3.0 3.3 3.6 4.3 5.2 1 0.5 0.7 1.
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STM32F411xC STM32F411xE Electrical characteristics Table 21. Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 3.
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Electrical characteristics STM32F411xC STM32F411xE Table 22. Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory- VDD = 1.
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STM32F411xC STM32F411xE Electrical characteristics Table 23. Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory - VDD = 3.
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Electrical characteristics STM32F411xC STM32F411xE Table 24. Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory - VDD = 3.
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STM32F411xC STM32F411xE Electrical characteristics Table 25. Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled with prefetch) running from Flash memory - VDD = 3.
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Electrical characteristics STM32F411xC STM32F411xE Table 26. Typical and maximum current consumption in Sleep mode - VDD = 3.6 V Symbol Parameter Conditions External clock, PLL ON(2), all peripherals enabled(3)(4) IDD Supply current in Sleep mode HSI, PLL OFF(2), all peripherals enabled(3) External clock, PLL ON(2) all peripherals disabled(3) HSI, PLL OFF(2), all peripherals disabled(3) Max(1) fHCLK (MHz) Typ 100 TA = TA = Unit 105 °C 125 °C TA = 25 °C TA = 85 °C 12.2 13.2 13.4 14.
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STM32F411xC STM32F411xE Electrical characteristics Table 28. Typical and maximum current consumption in Stop mode - VDD=3.6 V Max(1) Typ Symbol Conditions Parameter Flash in Stop mode, all Main regulator usage oscillators OFF, no independent watchdog Low power regulator usage IDD_STOP Flash in Deep power down mode, all oscillators OFF, no independent watchdog Main regulator usage TA = TA = TA = TA = TA = 25 °C 25 °C 85 °C 105 °C 125 °C 113.7 145(2) 410 720(2) 1217 43.
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Electrical characteristics STM32F411xC STM32F411xE Table 31. Typical and maximum current consumptions in VBAT mode Max(2) Typ Symbol TA = TA = TA = 85 °C 105 °C 125 °C Unit TA = 25 °C Conditions(1) Parameter VBAT = VBAT= VBAT = 1.7 V 2.4 V 3.3 V Backup domain IDD_VBAT supply current VBAT = 3.6 V Low-speed oscillator (LSE in lowdrive mode) and RTC ON 0.7 0.8 1.0 3 5 6.8 Low-speed oscillator (LSE in highdrive mode) and RTC ON 1.5 1.6 1.9 3.8 5.8 8.6 RTC and LSE OFF 0.1 0.1 0.
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STM32F411xC STM32F411xE Electrical characteristics I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 53: I/O static characteristics.
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Electrical characteristics STM32F411xC STM32F411xE Table 32. Switching output I/O current consumption Symbol Parameter Conditions(1) VDD = 3.3 V C = CINT VDD = 3.3 V CEXT = 0 pF C = CINT + CEXT + CS IDDIO I/O switching current VDD = 3.3 V CEXT =10 pF C = CINT + CEXT + CS VDD = 3.3 V CEXT = 22 pF C = CINT + CEXT + CS VDD = 3.3 V CEXT = 33 pF C = CINT + CEXT + CS I/O toggling Typ frequency (fSW) 2 MHz 0.05 8 MHz 0.15 25 MHz 0.45 50 MHz 0.85 60 MHz 1.00 84 MHz 1.40 90 MHz 1.
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STM32F411xC STM32F411xE Electrical characteristics On-chip peripheral current consumption The MCU is placed under the following conditions: • At startup, all I/O pins are in analog input configuration. • All peripherals are disabled unless otherwise mentioned. • The ART accelerator is ON. • Voltage Scale 2 mode selected, internal digital voltage V12 = 1.26 V. • HCLK is the system clock at 84 MHz. fPCLK1 = fHCLK/2, and fPCLK2 = fHCLK.
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Electrical characteristics STM32F411xC STM32F411xE Table 33. Peripheral current consumption (continued) Peripheral APB2 (up to 100 MHz) IDD (Typ) TIM1 5.71 TIM9 2.86 TIM10 1.79 TIM11 2.02 OTG_FS 23.93 ADC1(4) 2.98 SPI1 1.19 USART1 3.10 USART6 2.86 SDIO 5.95 SPI4 1.31 SYSCFG 0.71 Unit µA/MHz 1. Valid if all the DMA streams are activated (please refer to the reference manual RM0383). 2. For N DMA streams activated (up to 8 activated streams, refer to the reference manual RM0383).
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STM32F411xC STM32F411xE 6.3.7 Electrical characteristics Wakeup time from low-power modes The wakeup times given in Table 34 are measured starting from the wakeup event trigger up to the first instruction executed by the CPU: • For Stop or Sleep modes: the wakeup event is WFE. • WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes. Figure 21. Low-power mode wakeup :DNHXS IURP 6WRS PRGH PDLQ UHJXODWRU 2SWLRQ E\WHV DUH QRW UHORDGHG &38 UHVWDUW 5HJXODWRU +6, UHVWDUW )ODVK VWRS H[LW UDP
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Electrical characteristics STM32F411xC STM32F411xE Table 34. Low-power mode wakeup timings(1) Min(1) Typ(1) Max(1) Unit Wakeup from Sleep mode - 4 6 CPU clock cycle Wakeup from Stop mode, usage of main regulator - 13.5 14.
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STM32F411xC STM32F411xE Electrical characteristics Figure 22. High-speed external clock source AC timing diagram WZ +6(+ 9+6(+ 9+6(/ WU +6( WI +6( W WZ +6(/ 7+6( 06Y 9 Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 53. However, the recommended clock input waveform is shown in Figure 23.
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Electrical characteristics STM32F411xC STM32F411xE Figure 23. Low-speed external clock source AC timing diagram WZ /6(+ 9/6(+ 9/6(/ WU /6( WI /6( W WZ /6(/ 7/6( 06Y 9 High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator.
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STM32F411xC STM32F411xE Electrical characteristics Figure 24. Typical application with an 8 MHz crystal 5HVRQDWRU ZLWK LQWHJUDWHG FDSDFLWRUV &/ I+6( 26&B,1 0+] UHVRQDWRU &/ 5(;7 5) %LDV FRQWUROOHG JDLQ 26&B28 7 670 ) DL 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator.
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Electrical characteristics STM32F411xC STM32F411xE Figure 25. Typical application with a 32.768 kHz crystal 5HVRQDWRU ZLWK LQWHJUDWHG FDSDFLWRUV &/ I/6( 26& B,1 %LDV 5) FRQWUROOHG JDLQ N+ ] UHVRQDWRU 26& B28 7 &/ 670 ) DL 6.3.9 Internal clock source characteristics The parameters given in Table 39 and Table 40 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. High-speed internal (HSI) RC oscillator Table 39.
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STM32F411xC STM32F411xE Electrical characteristics Figure 26. ACCHSI versus temperature !##(3) 4! # -IN -AX 4YPICAL -3 6 1. Guaranteed by characterization results. Low-speed internal (LSI) RC oscillator Table 40. LSI oscillator characteristics (1) Symbol fLSI(2) tsu(LSI) (3) IDD(LSI)(3) Parameter Min Typ Max Unit 17 32 47 kHz LSI oscillator startup time - 15 40 µs LSI oscillator power consumption - 0.4 0.
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Electrical characteristics STM32F411xC STM32F411xE Figure 27. ACCLSI versus temperature MAX AVG MIN .ORMALIZED DEVIATI ON 4EMPERAT URE # -3 6 6.3.10 PLL characteristics The parameters given in Table 41 and Table 42 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 14. Table 41.
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STM32F411xC STM32F411xE Electrical characteristics Table 41. Main PLL characteristics (continued) Symbol Parameter Conditions Min Typ Max IDD(PLL)(4) PLL power consumption on VDD VCO freq = 100 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 IDDA(PLL)(4) PLL power consumption on VDDA VCO freq = 100 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 Unit mA 1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values.
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Electrical characteristics 6.3.11 STM32F411xC STM32F411xE PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 49: EMI characteristics for LQFP100). It is available only on the main PLL. Table 43. SSCG parameter constraints Symbol Parameter Min Typ Max(1) Unit fMod Modulation frequency - - 10 kHz md Peak modulation depth 0.
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STM32F411xC STM32F411xE Electrical characteristics Figure 28 and Figure 29 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 28. PLL output clock waveforms in center spread mode &REQUENCY 0,,?/54 MD & MD TMODE 4IME XTMODE AI Figure 29. PLL output clock waveforms in down spread mode )UHTXHQF\ 3//B287 ) [PG WPRGH 7LPH [WPRGH DL E 6.3.
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Electrical characteristics STM32F411xC STM32F411xE Table 45.
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STM32F411xC STM32F411xE Electrical characteristics Table 46. Flash memory programming with VPP voltage (continued) Symbol Parameter Conditions Min(1) Typ Max(1) Unit 2.7 - 3.6 V Vprog Programming voltage VPP VPP voltage range 7 - 9 V IPP Minimum current sunk on the VPP pin 10 - - mA - - 1 hour tVPP(3) Cumulative time during which VPP is applied 1. Guaranteed by design. 2. The maximum programming time is measured after 100K erase operations. 3.
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Electrical characteristics STM32F411xC STM32F411xE Table 48. EMS characteristics for LQFP100 package Symbol Parameter Conditions Level/ Class VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, LQFP100, WLCSP49, TA = +25 °C, fHCLK = 100 MHz, conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.
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STM32F411xC STM32F411xE Electrical characteristics Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Table 49. EMI characteristics for LQFP100 Symbol Parameter Max vs. [fHSE/fCPU] Monitored frequency band Conditions Unit 8/84 MHz SEMI 6.3.14 Peak level VDD = 3.
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Electrical characteristics STM32F411xC STM32F411xE Static latchup Two complementary static tests are required on six parts to assess the latchup performance: • • A supply overvoltage is applied to each power supply pin A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latchup standard. Table 51. Electrical sensitivities Symbol LU 6.3.
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STM32F411xC STM32F411xE Electrical characteristics Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. 6.3.16 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 53 are derived from tests performed under the conditions summarized in Table 14. All I/Os are CMOS and TTL compliant. Table 53.
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Electrical characteristics STM32F411xC STM32F411xE Table 53. I/O static characteristics (continued) Symbol RPU RPD CIO(8) Parameter Weak pull-up equivalent resistor(6) Weak pull-down equivalent resistor(7) Conditions Min Typ Max All pins except for PA10 (OTG_FS_ID) VIN = VSS 30 40 50 PA10 (OTG_FS_ID) - 7 10 14 All pins except for PA10 (OTG_FS_ID) VIN = VDD 30 40 50 PA10 (OTG_FS_ID) - 7 10 14 - - 5 - I/O pin capacitance Unit kΩ pF 1. Guaranteed by test in production.
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STM32F411xC STM32F411xE Electrical characteristics Figure 30.
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Electrical characteristics STM32F411xC STM32F411xE Output voltage levels Unless otherwise specified, the parameters given in Table 54 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. All I/Os are CMOS and TTL compliant. Table 54.
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STM32F411xC STM32F411xE Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 31 and Table 55, respectively. Unless otherwise specified, the parameters given in Table 55 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 55.
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Electrical characteristics STM32F411xC STM32F411xE Table 55. I/O AC characteristics(1)(2) (continued) OSPEEDRy [1:0] bit value(1) Symbol Parameter Conditions Fmax(IO)out Maximum frequency(3) 11 - tf(IO)out/ tr(IO)out tEXTIpw Output high to low level fall time and output low to high level rise time Min Typ Max CL = 30 pF, VDD ≥ 2.70 V - - 100(4) CL = 30 pF, VDD ≥ 1.7 V - - 50(4) CL = 30 pF, VDD ≥ 2.70 V - - 4 CL = 30 pF, VDD ≥ 1.7 V - - 6 CL = 10 pF, VDD≥ 2.70 V - - 2.
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STM32F411xC STM32F411xE 6.3.17 Electrical characteristics NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 53). Unless otherwise specified, the parameters given in Table 56 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 14. Refer to Table 53: I/O static characteristics for the values of VIH and VIL for NRST pin. Table 56.
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Electrical characteristics 6.3.18 STM32F411xC STM32F411xE TIM timer characteristics The parameters given in Table 57 are guaranteed by design. Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 57.
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STM32F411xC STM32F411xE Electrical characteristics Table 58. I2C characteristics Symbol Parameter Standard mode I2C(1)(2) Fast mode I2C(1)(2) Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - th(SDA) SDA data hold time 0 3450(3) 0 900(4) tr(SDA) tr(SCL) SDA and SCL rise time - 1000 - 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 th(STA) Start condition hold time 4.
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Electrical characteristics STM32F411xC STM32F411xE Figure 33. I2C bus AC waveforms and measurement circuit 9''B, & 9''B, & 53 53 670 56 6'$ ,ð& EXV 56 6&/ 67$57 5(3($7(' 67$57 67$57 WVX 67$ 6'$ WI 6'$ WU 6'$ WK 67$ WVX 6'$ WK 6'$ WZ 6&// 6&/ WZ 6&/+ WU 6&/ WI 6&/ WZ 672 67$ 6 723 WVX 672 DL G 1. RS = series protection resistor. 2. RP = external pull-up resistor. 3. VDD_I2C is the I2C bus power supply. Table 59. SCL frequency (fPCLK1= 50 MHz, VDD = VDD_I2C = 3.
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STM32F411xC STM32F411xE Electrical characteristics SPI interface characteristics Unless otherwise specified, the parameters given in Table 60 for the SPI interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.
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Electrical characteristics STM32F411xC STM32F411xE Table 60. SPI dynamic characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit ta(SO) Data output access time Slave mode 7 - 21 ns tdis(SO) Data output disable time Slave mode 5 - 12 ns Slave mode (after enable edge), 2.7 V < VDD < 3.6 V - 11 13 ns Slave mode (after enable edge), 1.7 V < VDD < 3.6 V - 11 18.5 ns tv(SO) Data output valid time th(SO) Data output hold time Slave mode (after enable edge), 1.
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STM32F411xC STM32F411xE Electrical characteristics Figure 35. SPI timing diagram - slave mode and CPHA = 1(1) 166 LQSXW 6&. LQSXW W68 166 &3+$ &32/ &3+$ &32/ WK 166 WF 6&. WZ 6&.+ WZ 6&./ WK 62 WY 62 WD 62 0,62 287387 06% 287 %,7 287 WGLV 62 /6% 287 WK 6, WVX 6, 026, ,1387 WU 6&. WI 6&. 06% ,1 /6% ,1 %,7 ,1 DL E Figure 36. SPI timing diagram - master mode(1) +LJK 166 LQSXW 6&. 2XWSXW &3+$ &32/ 6&. 2XWSXW WF 6&.
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Electrical characteristics STM32F411xC STM32F411xE I2S interface characteristics Unless otherwise specified, the parameters given in Table 61 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.
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STM32F411xC STM32F411xE Electrical characteristics Figure 37. I2S slave timing diagram (Philips protocol)(1) &. ,QSXW WF &. &32/ &32/ WZ &.+ WK :6 WZ &./ :6 LQSXW WY 6'B67 WVX :6 6'WUDQVPLW /6% WUDQVPLW 06% WUDQVPLW WVX 6'B65 /6% UHFHLYH 6'UHFHLYH WK 6'B67 %LWQ WUDQVPLW /6% WUDQVPLW WK 6'B65 06% UHFHLYH %LWQ UHFHLYH /6% UHFHLYH DL E 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 38.
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Electrical characteristics STM32F411xC STM32F411xE USB OTG full speed (FS) characteristics This interface is present in USB OTG FS controller. Table 62. USB OTG FS startup time Symbol tSTARTUP(1) Parameter USB OTG FS transceiver startup time Max Unit 1 µs 1. Guaranteed by design. Table 63. USB OTG FS DC electrical characteristics Symbol VDD Input levels Parameter Conditions USB OTG FS operating voltage Min.(1) Typ. Max.(1) Unit 3.0(2) - 3.
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STM32F411xC STM32F411xE Electrical characteristics Figure 39. USB OTG FS timings: definition of data signal rise and fall time &URVV RYHU SRLQWV 'LIIHUHQWLDO GDWD OLQHV 9&56 966 WI WU DL E Table 64. USB OTG FS electrical characteristics(1) Driver characteristics Symbol tr Parameter Rise tf Fall trfm time(2) time(2) Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 110 % 1.3 2.0 V Rise/ fall time matching VCRS Output signal crossover voltage 1.
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Electrical characteristics STM32F411xC STM32F411xE Table 65. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit - - 0.100 µs - - 3(5) 1/fADC - - 0.067 µs - - 2(5) 1/fADC 0.100 - 16 µs 3 - 480 1/fADC - 2 3 µs fADC = 30 MHz 12-bit resolution 0.50 - 16.40 µs fADC = 30 MHz 10-bit resolution 0.43 - 16.34 µs fADC = 30 MHz 8-bit resolution 0.37 - 16.27 µs fADC = 30 MHz 6-bit resolution 0.30 - 16.
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STM32F411xC STM32F411xE Electrical characteristics Equation 1: RAIN max formula R AIN ( k – 0.5 ) - – R ADC = --------------------------------------------------------------N+2 f ADC × C ADC × ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. Table 66.
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Electrical characteristics STM32F411xC STM32F411xE Table 69. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions(1) Symbol Parameter Test conditions ENOB Effective number of bits SINAD Signal-to-noise and distortion ratio SNR Signal-to-noise ratio THD Total harmonic distortion fADC =18 MHz VDDA = VREF+= 1.7 V Input Frequency = 20 KHz Temperature = 25 °C Min Typ Max Unit 10.3 10.4 - bits 64 64.2 - 64 65 - - -72 -67 dB 1. Guaranteed by characterization results.
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STM32F411xC STM32F411xE Electrical characteristics Figure 40. ADC accuracy characteristics ; ,3" )$%!, 6 2%& OR 6 $$! DEPENDING ON PACKAGE = %' %4 %/ %, %$ , 3")$%!, 6 33! 6$$! AI C 1. See also Table 67. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line. 5.
PAGE 118
Electrical characteristics STM32F411xC STM32F411xE General PCB design guidelines Power supply decoupling should be performed as shown in Figure 42 or Figure 43, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 42. Power supply and reference decoupling (VREF+ not connected to VDDA) 670 ) 95() ) Q) 9''$ ) Q) 966$ 95() DL E 1.
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STM32F411xC STM32F411xE Electrical characteristics Figure 43. Power supply and reference decoupling (VREF+ connected to VDDA) 670 ) 95() 9''$ ) Q) 95() 966$ DL F 1. VREF+ and VREF- inputs are both available on UFBGA100. VREF+ is also available on LQFP100. When VREF+ and VREF- are not available, they are internally connected to VDDA and VSSA. 6.3.21 Temperature sensor characteristics Table 71.
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Electrical characteristics 6.3.22 STM32F411xC STM32F411xE VBAT monitoring characteristics Table 73. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit KΩ R Resistor bridge for VBAT - 50 - Q Ratio on VBAT measurement - 4 - Error on Q –1 - +1 % ADC sampling time when reading the VBAT 1 mV accuracy 5 - - µs (1) Er TS_vbat(2)(2) 1. Guaranteed by design. 2. Shortest sampling time can be determined in the application by multiple iterations. 6.3.
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STM32F411xC STM32F411xE 6.3.
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Electrical characteristics STM32F411xC STM32F411xE Table 76. Dynamic characteristics: SD / MMC characteristics(1)(2) Symbol fPP - Parameter Conditions Min Typ Max Unit Clock frequency in data transfer mode - 0 - 50 MHz SDIO_CK/fPCLK2 frequency ratio - - - 8/3 - tW(CKL) Clock low time fpp = 50 MHz 10.5 11 - tW(CKH) Clock high time fpp = 50 MHz 8.5 9 - fpp = 50 MHz 2.5 - - fpp = 50 MHz -40°C
PAGE 123
STM32F411xC STM32F411xE 6.3.25 Electrical characteristics RTC characteristics Table 77. Dynamic characteristics: eMMC characteristics VDD = 1.7 V to 1.9 V(1)(2) Symbol fPP - Parameter Conditions Min Typ Max Unit Clock frequency in data transfer mode - 0 - 50 MHz SDIO_CK/fPCLK2 frequency ratio - - - 8/3 - tW(CKL) Clock low time fpp = 50 MHz 10 10.5 - tW(CKH) Clock high time fpp = 50 MHz 9 9.
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Package information 7 STM32F411xC STM32F411xE Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 WLCSP49 package information Figure 46. WLCSP49 - 49-ball, 2.999 x 3.185 mm, 0.
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STM32F411xC STM32F411xE Package information Table 79. WLCSP49 - 49-ball, 2.999 x 3.185 mm, 0.4 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.175 - - 0.0069 - A2 - 0.380 - - 0.0150 - A3 (2) - 0.025 - - 0.0010 - (3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 2.964 2.999 3.034 0.1167 0.1181 0.1194 E 3.150 3.185 3.220 0.1240 0.1254 0.
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Package information STM32F411xC STM32F411xE Table 80. WLCSP49 recommended PCB design rules (0.4 mm pitch) Dimension Recommended values Pitch 0.4 mm Dpad 260 µm max. (circular) 220 µm recommended Dsm 300 µm min. (for 260 µm diameter pad) PCB pad design Non-solder mask defined via underbump allowed Device marking for WLCSP49 The following figure gives an example of topside marking orientation versus ball A1 identifier location.
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STM32F411xC STM32F411xE 7.2 Package information UFQFPN48 package information Figure 49. UFQFPN48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline 3LQ LGHQWLILHU ODVHU PDUNLQJ DUHD ' $ ( ( 7 GGG $ 6HDWLQJ SODQH E H 'HWDLO < ' ([SRVHG SDG DUHD < ' / & [ SLQ FRUQHU 5 W\S 'HWDLO = ( = $ % B0(B9 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3.
PAGE 128
Package information STM32F411xC STM32F411xE Table 81. UFQFPN48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 T - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - ddd - - 0.080 - - 0.0031 1.
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STM32F411xC STM32F411xE Package information Device marking for UFQFPN48 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 51. UFQFPN48 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ 670 ) &(8 'DWH FRGH < :: 3LQ LQGHQWLILHU 5HYLVLRQ FRGH 5 06Y 9 1.
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Package information 7.3 STM32F411xC STM32F411xE LQFP64 package information Figure 52. LQFP64 - 64-pin, 10 x 10 mm, 64-pin low-profile quad flat package outline PP *$8*( 3/$1( F $ $ $ 6($7,1* 3/$1( & $ FFF & ' ' ' . / / 3,1 ,'(17,),&$7,21 ( ( ( E H :B0(B9 1. Drawing is not to scale. 130/149 Downloaded from Arrow.com.
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STM32F411xC STM32F411xE Package information Table 82. LQFP64 - 64-pin, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - E - 12.000 - - 0.
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Package information STM32F411xC STM32F411xE Device marking for LQFP64 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 54. LQFP64 marking example (package top view) 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ 5 670 ) 5(7 'DWH FRGH < :: 3LQ LQGHQWLILHU 06Y 9 1.
PAGE 133
STM32F411xC STM32F411xE 7.4 Package information LQFP100 package information Figure 55. LQFP100 - 100-pin, 14 x 14 mm, 100-pin low-profile quad flat package outline MM C ! ! ! 3%!4).' 0,!.% # '!5'% 0,!.% $ , $ ! + CCC # , $ 0). )$%.4)&)#!4)/. % % % B E ,?-%?6 1. Drawing is not to scale. DocID026289 Rev 6 133/149 141 Downloaded from Arrow.com.
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Package information STM32F411xC STM32F411xE Table 83. LQPF100 - 100-pin, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. A - - 1.60 - - 0.063 A1 0.050 - 0.150 0.002 - 0.0059 A2 1.350 1.40 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.622 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.
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STM32F411xC STM32F411xE Package information Figure 56. LQFP100 - 100-pin, 14 x 14 mm, 100-pin low-profile quad flat recommended footprint AI C 1. Dimensions are in millimeters. DocID026289 Rev 6 135/149 141 Downloaded from Arrow.com.
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Package information STM32F411xC STM32F411xE Device marking for LQFP100 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 57. LQPF100 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ (6 ) 2SWLRQDO JDWH PDUN 9(7 $ 5HYLVLRQ FRGH 'DWH FRGH < :: 3LQ LQGHQWLILHU 06Y 9 1.
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STM32F411xC STM32F411xE 7.5 Package information UFBGA100 package information Figure 58. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline = 6HDWLQJ SODQH GGG = $ $ $ $ $ ( H $ EDOO $ EDOO LGHQWLILHU LQGH[ DUHD ) ; ( $ ) ' ' H < 0 %27720 9,(: E EDOOV HHH 0 = < ; III 0 = 723 9,(: $ & B0(B9 1. Drawing is not to scale. Table 84. UFBGA100, 7 x 7 mm, 0.
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Package information STM32F411xC STM32F411xE Table 84. UFBGA100, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 59. Recommended PCB design rules for pads (0.
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STM32F411xC STM32F411xE Package information Device marking for UFBGA100 The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 60. UFBGA100 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ (6 ) 9(, 'DWH FRGH < :: %DOO LQGHQWLILHU 5HYLVLRQ FRGH 5 06Y 9 1.
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Package information 7.6 STM32F411xC STM32F411xE Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 14: General operating conditions on page 59. The maximum chip-junction temperature, TJ max.
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STM32F411xC STM32F411xE 8 Part numbering Part numbering Table 86.
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Recommendations when using the internal reset OFF Appendix A STM32F411xC STM32F411xE Recommendations when using the internal reset OFF When the internal reset is OFF, the following integrated features are no longer supported: A.1 • The integrated power-on-reset (POR)/power-down reset (PDR) circuitry is disabled. • The brownout reset (BRO) circuitry must be disabled. By default BOR is OFF. • The embedded programmable voltage detector (PVD) is disabled.
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STM32F411xC STM32F411xE Appendix B B.1 Application block diagrams Application block diagrams USB OTG Full Speed (FS) interface solutions Figure 61. USB controller configured as peripheral-only and used in Full-Speed mode 9'' 9 WR 9'' 9ROWDJH UHJXODWRU 9%86 26&B,1 '0 3$ '3 3$ 966 26&B287 86% 6WG % FRQQHFWRU 670 ) [&[( 06 9 1. The external voltage regulator is only needed when building a VBUS powered device. Figure 62.
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Application block diagrams STM32F411xC STM32F411xE Figure 63. USB controller configured in dual mode and used in Full-Speed mode 9'' 9 WR 9'' YROWDJH UHJXODWRU 9'' *3,2 *3,2 ,54 (1 &XUUHQW OLPLWHU 2YHUFXUUHQW SRZHU VZLWFK 9 SRZHU 3$ 9%86 3$ 26&B,1 26&B287 3$ 3$ '0 '3 ,' 966 86%QLFUR $% FRQQHFWRU 670 ) [&[( 06 9 1. The external voltage regulator is only needed when building a VBUS powered device. 2.
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STM32F411xC STM32F411xE B.2 Application block diagrams Sensor Hub application example Figure 64. Sensor Hub application example $FFHOHURPHWHU *\URVFRSH 0DJQHWRPHWHU 670 ) [( DQG SLQ SDFNDJH 3% 3% 3$ 6&/ , & 3UHVVXUH 3% 3% 3% 6'$ [ *3,2 N 3% *3,2 6/. 3UR[LPLW\ %227 3$ 7; 9'' 3'521 3$ 166 6:2 3$ 6&. 3% 1567 8$57 0LFUR 3$ 5; 6:',2 3$ -7$* 6:&/.
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Application block diagrams B.3 STM32F411xC STM32F411xE Batch Acquisition Mode (BAM) example Data is transferred through the DMA from interfaces into the internal SRAM while the rest of the MCU is set in low power mode. • Code execution from RAM before switching off the Flash. • Flash is set in power down and flash interface (ART™ accelerator) clock is stopped. • The clocks are enabled only for the required interfaces. • MCU core is set in sleep mode (core clock stopped waiting for interrupt).
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STM32F411xC STM32F411xE Revision history Revision history Table 88. Document revision history Date Revision 19-Jun-2014 1 Initial release. 2 Introduced the BAM feature in Features, Section 2: Description., and Section 3.3: Batch Acquisition mode (BAM). Updated Section 3.5: Embedded Flash memory, Section 3.14: Power supply schemes and Section 3.18: Low-power modes, Section 3.20.2: General-purpose timers (TIMx) and Section 3.30: Temperature sensor.
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Revision history STM32F411xC STM32F411xE Table 88. Document revision history Date 21-Nov-2016 05-Dec-2016 148/149 Downloaded from Arrow.com.
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